Microchip Technology DV164136 Data Sheet
© 2008 Microchip Technology Inc.
DS39646C-page 227
PIC18F8722 FAMILY
FIGURE 19-13:
I
2
C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
x
SCL
x
S
S
P
x
IF
(P
IR1<
3>
or
P
IR3
<
7
>
)
BF
(
S
SPx
S
T
A
T
<0
>)
SSP
O
V
(
S
SPx
CO
N1
<6
>)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
A
7
A6
A
5
A4
A
3
A
2
A
1
D7
D6
D5
D4
D3
D2
D1
D
0
D7
D6
D
5
D4
D3
D1
D0
ACK
Re
ce
ivin
g
Da
ta
ACK
Re
ce
ivin
g
Da
ta
R/W
=
0
ACK
R
e
cei
v
ing A
ddr
ess
Cle
a
re
d
in
so
ft
wa
re
SSP
xBUF
is
re
a
d
B
u
s m
a
st
er
ter
m
inate
s
tra
n
sfer
S
SPO
V
is
s
e
t
b
e
c
a
u
s
e
SS
Px
BUF
is
still fu
ll. ACK
is n
o
t sent
.
D2
6
CK
P
CK
P
wr
itte
n
to ‘
1
’ in
If B
F
i
s
cleare
d
pr
ior to
the fa
llin
g
edg
e of t
h
e 9th
cl
ock,
CKP
will n
o
t b
e
r
e
se
t
to ‘
0
’ a
nd no
cl
ock
str
e
tch
in
g
will o
ccu
r
softwar
e
Clo
ck
is
h
e
ld
lo
w u
n
til
CK
P
is set to
‘
1
’
Clo
ck is n
o
t h
e
ld
lo
w
be
cause b
u
ff
er
ful
l bi
t i
s
cle
a
r p
ri
o
r to
fa
llin
g
e
d
g
e
of 9th
cl
ock
Clo
ck is n
o
t h
e
ld
lo
w
becau
s
e A
C
K
=
1
BF
i
s
se
t
a
fte
r
fa
llin
g
ed
g
e
of
t
h
e
9t
h
c
lo
c
k
,
CK
P
is rese
t to ‘
0
’ a
n
d
clock str
e
tch
ing
occu
rs