Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 264
© 2008 Microchip Technology Inc.
20.3
EUSART Synchronous
Master Mode
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTAx<4>). In addition, enable bit SPEN
(RCSTAx<7>) is set in order to configure the TXx and
RXx pins to CKx (clock) and DTx (data) lines,
respectively.
the CSRC bit (TXSTAx<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTAx<4>). In addition, enable bit SPEN
(RCSTAx<7>) is set in order to configure the TXx and
RXx pins to CKx (clock) and DTx (data) lines,
respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CKx line. Clock polarity is
selected with the SCKP bit (BAUDCONx<4>); setting
SCKP sets the Idle state on CKx as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
mits the master clock on the CKx line. Clock polarity is
selected with the SCKP bit (BAUDCONx<4>); setting
SCKP sets the Idle state on CKx as high, while clearing
the bit sets the Idle state as low. This option is provided
to support Microwire devices with this module.
20.3.1
EUSART SYNCHRONOUS MASTER
TRANSMISSION
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSRx). The Shift register
obtains its data from the Read/Write Transmit Buffer
register, TXREGx. The TXREGx register is loaded with
data in software. The TSRx register is not loaded until
the last bit has been transmitted from the previous load.
As soon as the last bit is transmitted, the TSRx is
loaded with new data from the TXREGx (if available).
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSRx). The Shift register
obtains its data from the Read/Write Transmit Buffer
register, TXREGx. The TXREGx register is loaded with
data in software. The TSRx register is not loaded until
the last bit has been transmitted from the previous load.
As soon as the last bit is transmitted, the TSRx is
loaded with new data from the TXREGx (if available).
Once the TXREGx register transfers the data to the
TSRx register (occurs in one T
TSRx register (occurs in one T
CY
), the TXREGx is
empty and the TXxIF flag bit is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXxIE. TXxIF is set regardless of the state
of enable bit TXxIE; it cannot be cleared in software. It
will reset only when new data is loaded into the
TXREGx register.
enabled or disabled by setting or clearing the interrupt
enable bit, TXxIE. TXxIF is set regardless of the state
of enable bit TXxIE; it cannot be cleared in software. It
will reset only when new data is loaded into the
TXREGx register.
While flag bit TXxIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSRx register. TRMT is a read-only bit
which is set when the TSRx is empty. No interrupt logic
is tied to this bit, so the user must poll this bit in order to
determine if the TSRx register is empty. The TSRx is not
mapped in data memory so it is not available to the user.
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSRx register. TRMT is a read-only bit
which is set when the TSRx is empty. No interrupt logic
is tied to this bit, so the user must poll this bit in order to
determine if the TSRx register is empty. The TSRx is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1.
Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
setting bits SYNC, SPEN and CSRC.
3.
If interrupts are desired, set enable bit TXxIE.
4.
If 9-bit transmission is desired, set bit TX9.
5.
Enable the transmission by setting bit TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
should be loaded in bit TX9D.
7.
Start transmission by loading data to the
TXREGx register.
TXREGx register.
8.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-11:
SYNCHRONOUS TRANSMISSION
bit 0
bit 1
bit 7
Word 1
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2
bit 0
bit 1
bit 7
DTx
CKx pin
Write to
TXREGx Reg
TXREGx Reg
TXxIF bit
(Interrupt Flag)
(Interrupt Flag)
TXEN bit ‘
1
’
‘
1
’
Word 2
TRMT bit
Write Word 1
Write Word 2
Note:
Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words.
CKx pin
(SCKP =
0
)
(SCKP =
1
)