Microchip Technology DV164136 Data Sheet
© 2008 Microchip Technology Inc.
DS39646C-page 35
PIC18F8722 FAMILY
2.6.4
PLL IN INTOSC MODES
The 4x Phase Locked Loop (PLL) can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator sources. When enabled, the PLL produces a
clock speed of 16 MHz or 32 MHz.
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator sources. When enabled, the PLL produces a
clock speed of 16 MHz or 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC<3:0> = 1001 or 1000). Additionally, the
PLL will only function when the selected output fre-
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled and the PLLEN bit remains clear (writes are
ignored).
use the internal oscillator block as its primary clock
source (FOSC<3:0> = 1001 or 1000). Additionally, the
PLL will only function when the selected output fre-
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled and the PLLEN bit remains clear (writes are
ignored).
2.6.5
INTOSC FREQUENCY DRIFT
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as V
output (INTOSC) for 8 MHz. However, this frequency
may drift as V
DD
or temperature changes and can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. Depending on the
device, this may have no effect on the INTRC clock
source frequency.
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. Depending on the
device, this may have no effect on the INTRC clock
source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are discussed
in
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are discussed
in
EUSART”, Section 2.6.5.2 “Compensating with the
Timers” and Section 2.6.5.3 “Compensating with the
CCP Module in Capture Mode” but other techniques
may be used.
Timers” and Section 2.6.5.3 “Compensating with the
CCP Module in Capture Mode” but other techniques
may be used.
REGISTER 2-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0
U-0
R/W-0
R/W-0 R/W-0 R/W-0 R/W-0
INTSRC
PLLEN
(1)
—
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1
= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0
= 31 kHz device clock derived directly from INTRC internal oscillator
bit 6
PLLEN: Frequency Multiplier PLL for INTOSC Enable bit
(1)
1
= PLL enabled for INTOSC (4 MHz and 8 MHz only)
0
= PLL disabled
bit 5
Unimplemented: Read as ‘0’
bit 4-0
TUN<4:0>: Frequency Tuning bits
01111
= Maximum frequency
•
•
•
•
00001
00000
= Center frequency. Oscillator module is running at the calibrated frequency.
11111
•
•
•
•
10000
= Minimum frequency
Note 1:
Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See
Section 2.6.4 “PLL in INTOSC Modes” for details.
Section 2.6.4 “PLL in INTOSC Modes” for details.