Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 38
© 2008 Microchip Technology Inc.
2.7.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<3:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after either of the SCS<1:0> bits are
changed, following a brief clock transition interval. The
SCS bits are reset on all forms of Reset.
clock source. The available clock sources are the
primary clock (defined by the FOSC<3:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after either of the SCS<1:0> bits are
changed, following a brief clock transition interval. The
SCS bits are reset on all forms of Reset.
The Internal Oscillator Frequency Select bits
(IRCF<2:0>) select the frequency output of the internal
oscillator block to drive the device clock. The choices
are the INTRC source (31 kHz), the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31.25 kHz to 4 MHz). If the
internal oscillator block is supplying the device clock,
changing the states of these bits will have an immedi-
ate change on the internal oscillator’s output. On
device Resets, the default output frequency of the
internal oscillator block is set at 1 MHz.
(IRCF<2:0>) select the frequency output of the internal
oscillator block to drive the device clock. The choices
are the INTRC source (31 kHz), the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31.25 kHz to 4 MHz). If the
internal oscillator block is supplying the device clock,
changing the states of these bits will have an immedi-
ate change on the internal oscillator’s output. On
device Resets, the default output frequency of the
internal oscillator block is set at 1 MHz.
When a nominal output frequency of 31 kHz is selected
(IRCF<2:0> = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source derived from the INTOSC postscaler. Clearing
INTSRC selects INTRC (nominally 31 kHz) as the
clock source and disables the INTOSC to reduce
current consumption.
(IRCF<2:0> = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source derived from the INTOSC postscaler. Clearing
INTSRC selects INTRC (nominally 31 kHz) as the
clock source and disables the INTOSC to reduce
current consumption.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Addition-
ally, the INTOSC source will already be stable should a
switch to a higher frequency be needed quickly.
Regardless of the setting of INTSRC, INTRC always
remains the clock source for features such as the
Watchdog Timer and the Fail-Safe Clock Monitor.
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Addition-
ally, the INTOSC source will already be stable should a
switch to a higher frequency be needed quickly.
Regardless of the setting of INTSRC, INTRC always
remains the clock source for features such as the
Watchdog Timer and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
and PLL Start-up Timer (if enabled) have timed out and
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
and PLL Start-up Timer (if enabled) have timed out and
the primary clock is providing the device clock in
primary clock modes. The IOFS bit indicates when the
internal oscillator block has stabilized and is providing
the device clock in RC Clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes.
In power-managed modes, only one of these three bits
will be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator
block has just started and is not yet stable.
primary clock modes. The IOFS bit indicates when the
internal oscillator block has stabilized and is providing
the device clock in RC Clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the device clock in secondary clock modes.
In power-managed modes, only one of these three bits
will be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator
block has just started and is not yet stable.
The IDLEN bit controls whether the device goes into
Sleep mode or one of the Idle modes when the SLEEP
instruction is executed.
Sleep mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
2.7.2
OSCILLATOR TRANSITIONS
The PIC18F8722 family of devices contains circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
Section 3.1.2 “Entering Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source will be ignored.
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.