Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 400
© 2008 Microchip Technology Inc.
FIGURE 28-7:
CLKO AND I/O TIMING
TABLE 28-9:
CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
T
OS
H2
CK
L OSC1
↑ to CLKO ↓ —
75
200
ns
(Note 1)
11
T
OS
H2
CK
H OSC1
↑ to CLKO ↑ —
75
200
ns
(Note 1)
12
T
CK
R
CLKO Rise Time
—
35
100
ns
(Note 1)
13
T
CK
F
CLKO Fall Time
—
35
100
ns
(Note 1)
14
T
CK
L2
IO
V
CLKO
↓ to Port Out Valid
—
—
0.5 T
CY
+ 20
ns
(Note 1)
15
T
IO
V2
CK
H Port In Valid before CLKO
↑ 0.25
T
CY
+ 25
—
—
ns
(Note 1)
16
T
CK
H2
IO
I
Port In Hold after CLKO
↑
0
—
—
ns
(Note 1)
17
T
OS
H2
IO
V OSC1
↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18
T
OS
H2
IO
I
OSC1
↑ (Q2 cycle) to
Port Input Invalid
(I/O in hold time)
(I/O in hold time)
PIC18FXXXX
100
—
—
ns
18A
PIC18LFXXXX
200
—
—
ns
V
DD
= 2.0V
19
T
IO
V2
OS
H Port Input Valid to OSC1
↑ (I/O in setup
time)
0
—
—
ns
20
T
IO
R
Port Output Rise Time
PIC18FXXXX
—
10
25
ns
20A
PIC18LFXXXX
—
—
60
ns
V
DD
= 2.0V
21
T
IO
F
Port Output Fall Time
PIC18FXXXX
—
10
25
ns
21A
PIC18LFXXXX
—
—
60
ns
V
DD
= 2.0V
22†
T
INP
INTx pin High or Low Time
T
CY
—
—
ns
23†
T
RBP
RB<7:4> Change INTx High or Low Time
T
CY
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1:
Measurements are taken in RC mode, where CLKO output is 4 x T
OSC
.
Note:
Refer to Figure 28-5 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2
Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value