Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 408
© 2008 Microchip Technology Inc.
FIGURE 28-16:
EXAMPLE SPI MASTER MODE TIMING (CKE =
1
)
TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE =
1
)
SSx
SCKx
(CKP =
(CKP =
0
)
SCKx
(CKP =
(CKP =
1
)
SDOx
SDIx
81
71
72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note:
Refer to Figure 28-5 for load conditions.
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
71
T
SC
H
SCKx Input High Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30
—
ns
71A
Single Byte
40
—
ns
(Note 1)
72
T
SC
L
SCKx Input Low Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30
—
ns
72A
Single Byte
40
—
ns
(Note 1)
73
T
DI
V2
SC
H,
T
DI
V2
SC
L
Setup Time of SDIx Data Input to SCKx Edge
20
—
ns
73A
T
B
2
B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
of Byte 2
1.5 T
CY
+ 40
—
ns
(Note 2)
74
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDIx Data Input to SCKx Edge
40
—
ns
75
T
DO
R
SDOx Data Output Rise Time PIC18FXXXX
—
25
ns
PIC18LFXXXX
—
45
ns
V
DD
= 2.0V
76
T
DO
F
SDOx Data Output Fall Time
—
25
ns
78
T
SC
R
SCKx Output Rise Time
(Master mode)
(Master mode)
PIC18FXXXX
—
25
ns
PIC18LFXXXX
—
45
ns
V
DD
= 2.0V
79
T
SC
F
SCKx Output Fall Time (Master mode)
—
25
ns
80
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDOx Data Output Valid after
SCKx Edge
SCKx Edge
PIC18FXXXX
—
50
ns
PIC18LFXXXX
—
100
ns
V
DD
= 2.0V
81
T
DO
V2
SC
H,
T
DO
V2
SC
L
SDOx Data Output Setup to SCKx Edge
T
CY
—
ns
Note 1:
Requires the use of Parameter #73A.
2:
Only if Parameter #71A and #72A are used.