Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 414
© 2008 Microchip Technology Inc.
TABLE 28-23: MASTER SSP I
2
C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
T
HIGH
Clock High Time 100 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
400 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
ms
101
T
LOW
Clock Low Time
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
400 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
ms
102
T
R
SDAx and SCLx
Rise Time
Rise Time
100 kHz mode
—
1000
ns
C
B
is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1 C
B
300
ns
1 MHz mode
(1)
—
300
ns
103
T
F
SDAx and SCLx
Fall Time
Fall Time
100 kHz mode
—
300
ns
C
B
is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1 C
B
300
ns
1 MHz mode
(1)
—
100
ns
90
T
SU
:
STA
Start Condition
Setup Time
Setup Time
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
Only relevant for
Repeated Start
condition
Repeated Start
condition
400 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
ms
91
T
HD
:
STA
Start Condition
Hold Time
Hold Time
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
After this period, the first
clock pulse is generated
clock pulse is generated
400 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
ms
106
T
HD
:
DAT
Data Input
Hold Time
Hold Time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
ms
1 MHz mode
(1)
TBD
—
ns
107
T
SU
:
DAT
Data Input
Setup Time
Setup Time
100 kHz mode
250
—
ns
(Note 2)
400 kHz mode
100
—
ns
1 MHz mode
(1)
TBD
—
ns
92
T
SU
:
STO
Stop Condition
Setup Time
Setup Time
100 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
400 kHz mode
2(T
OSC
)(BRG + 1)
—
ms
1 MHz mode
(1)
2(T
OSC
)(BRG + 1)
—
ms
109
T
AA
Output Valid
from Clock
from Clock
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
1 MHz mode
(1)
—
—
ns
110
T
BUF
Bus Free Time
100 kHz mode
4.7
—
ms
Time the bus must be free
before a new transmission
can start
before a new transmission
can start
400 kHz mode
1.3
—
ms
1 MHz mode
(1)
TBD
—
ms
D102
C
B
Bus Capacitive Loading
—
400
pF
Legend: TBD = To Be Determined
Note 1:
Maximum pin capacitance = 10 pF for all I
2
C™ pins.
2:
A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but parameter #107
≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode,) before
the SCLx line is released.
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data
bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode,) before
the SCLx line is released.