Microchip Technology DV164136 Data Sheet
© 2008 Microchip Technology Inc.
DS39646C-page 417
PIC18F8722 FAMILY
TABLE 28-27: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
130
T
AD
A/D Clock Period
PIC18FXXXX
0.7
25.0
(1)
μs
T
OSC
based, V
REF
≥ 3.0V
PIC18LFXXXX
1.4
25.0
(1)
μs
V
DD
= 2.0V;
T
OSC
based, V
REF
full range
PIC18FXXXX
—
1
μs
A/D RC mode
PIC18LFXXXX
—
3
μs
V
DD
= 2.0V; A/D RC mode
131
T
CNV
Conversion Time
(not including acquisition time) (Note 2)
(not including acquisition time) (Note 2)
11
12
T
AD
132
T
ACQ
Acquisition Time (Note 3)
1.4
—
μs
-40
°C to +85°C
135
T
SWC
Switching Time from Convert
→ Sample
—
(Note 4)
137
T
DIS
Discharge Time
0.2
—
μs
Legend: TBD = To Be Determined
Note 1:
The time of the A/D clock period is dependent on the device frequency and the T
AD
clock divider.
2:
ADRES register may be read on the following T
CY
cycle.
3:
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
after the conversion (V
DD
to V
SS
or V
SS
to V
DD
). The source impedance (R
S
) on the input channels is 50
Ω.
4:
On the following cycle of the device clock.