Microchip Technology DV164136 Data Sheet

© 2008 Microchip Technology Inc.

DS39646C-page 89

R/W-x

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

R/S-0

EEPGD

CFGS

—

FREE

WRERR

WREN

WR

RD

bit 7

bit 0

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EEPGD: Flash Program or Data EEPROM Memory Select bit

1

 = Access Flash program memory

0

 = Access data EEPROM memory

bit 6

CFGS: Flash Program/Data EEPROM or Configuration Select bit

1

 = Access Configuration registers

0

 = Access Flash program or data EEPROM memory

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit

1

 = Erase the program memory row addressed by TBLPTR on the next WR command 

(cleared by completion of erase operation)

0

 = Perform write only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit

1

 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0

 = The write operation completed

bit 2

WREN: Flash Program/Data EEPROM Write Enable bit

1

 = Allows write cycles to Flash program/data EEPROM

0

 = Inhibits write cycles to Flash program/data EEPROM

bit 1

WR: Write Control bit

1

 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. 

(The operation is self-timed and the bit is cleared by hardware once write is complete. 
The WR bit can only be set (not cleared) in software.)

0

 = Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1

 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0

 = Does not initiate an EEPROM read

When a WRERR occurs, the EEPGD and CFGS bits are not cleared. 
This allows tracing of the error condition.