Microchip Technology MA320001 Data Sheet
© 2011 Microchip Technology Inc.
DS61143H-page 105
PIC32MX3XX/4XX
14.0
TIMER2/3 AND TIMER4/5
This family of PIC32MX devices features four
synchronous 16-bit timers (default) that can operate as
a free-running interval timer for various timing applica-
tions and counting external events. The following
modes are supported:
synchronous 16-bit timers (default) that can operate as
a free-running interval timer for various timing applica-
tions and counting external events. The following
modes are supported:
• Synchronous Internal 16-bit Timer
• Synchronous Internal 16-bit Gated Timer
• Synchronous External 16-bit Timer
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
• Synchronous Internal 32-bit Timer
• Synchronous Internal 32-bit Gated Timer
• Synchronous External 32-bit Timer
14.1
Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU Idle
• Time base for input capture and output compare
modules (Timer2 and Timer3 only)
• ADC event trigger (Timer3 only)
• Fast bit manipulation using CLR, SET and INV
registers
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 14. “Timers” (DS61105)
of the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 14. “Timers” (DS61105)
of the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (
www.microchip.com/PIC32
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
Note:
Throughout this chapter, references to
registers TxCON, TMRx and PRx use ‘x’
to represent Timer2 through 5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or 4; ‘y’ represents Timer3 or 5.
registers TxCON, TMRx and PRx use ‘x’
to represent Timer2 through 5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or 4; ‘y’ represents Timer3 or 5.
Sync
PRx
TxIF
Equal
Comparator x 16
TMRx
Reset
Event Flag
Q
Q
D
TGATE (TxCON<7>)
1
0
Gate
TxCK
(2)
Sync
ON (TxCON<15>)
TGATE (TxCON<7>)
TCS (TxCON<1>)
TCKPS (TxCON<6:4>)
Prescaler
3
1, 2, 4, 8, 16,
32, 64, 256
x
1
1
0
0
0
PBCLK
Trigger
(1)
ADC Event
Note 1: ADC event trigger is available on Timer3 only.
2: TxCK pins not available on 64-pin devices.