Microchip Technology MA320001 Data Sheet

PIC32MX3XX/4XX

DS61143H-page 106

FIGURE 14-2:

TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)

TMRy

TMRx

TyIF Event

Equal

32-bit Comparator

PRy

PRx

Reset

LSHalfWord

MSHalfWord

Flag

Note 1: In this diagram, the use of ‘x’ in registers TxCON, TMRx, PRx and TxCK refers to either

Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5.

2: TxCK pins are not available on 64-pin devices.

3: ADC event trigger is available only on Timer2/3 pair.

TGATE (TxCON<7>)

PBCLK

Gate

TxCK

(2)

Sync

ADC Event
Trigger

(3)

ON (TxCON<15>)

TGATE (TxCON<7>)

TCS (TxCON<1>)

TCKPS (TxCON<6:4>)

Prescaler

1, 2, 4, 8, 16,

32, 64, 256