Microchip Technology DV164136 Data Sheet
2007-2012 Microchip Technology Inc.
DS39778E-page 11
PIC18F87J11 FAMILY
FIGURE 1-2:
PIC18F8XJ1X (80-PIN) BLOCK DIAGRAM
PRODL
PRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W
8
8
8
Instruction
Decode &
Control
Data Latch
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
Address Latch
Program Memory
(128 Kbytes)
Data Latch
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
ROM Latch
PCLATU
PCU
Instruction Bus <16>
STKPTR
Bank
State Machine
Control Signals
Control Signals
Decode
S
yste
m
B
u
s Int
er
face
AD<15:0>, A<19:16>
(Multiplexed with PORTD,
PORTE and PORTH)
(Multiplexed with PORTD,
PORTE and PORTH)
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA<7:0>
(1)
RC<7:0>
(1)
RD<7:0>
(1)
RE<7:0>
(1)
RF<7:2>
(1)
RG<4:0>
(1)
PORTB
RB<7:0>
(1)
PORTH
RH<7:0>
(1)
PORTJ
RJ<7:0>
(1)
EUSART1
Comparators
MSSP1
Timer2
Timer1
Timer3
Timer0
ECCP1
A/D
10-Bit
EUSART2
ECCP2
ECCP3
MSSP2
CCP4
CCP5
Timer4
Note
1:
for I/O port pin descriptions.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
Data Memory
(2.0, 3.9
Kbytes)
PMP
OSC1/CLKI
OSC2/CLKO
V
DD
, V
SS
8 MHz
INTOSC
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
V
DDCORE
/V
CAP
ENVREG
Timing
Generation