Microchip Technology DV164136 Data Sheet
2007-2012 Microchip Technology Inc.
DS39778E-page 289
PIC18F87J11 FAMILY
21.1
Baud Rate Generator (BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSARTx. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
The SPBRGHx:SPBRGx register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored.
supports both the Asynchronous and Synchronous
modes of the EUSARTx. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
The SPBRGHx:SPBRGx register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored.
shows the formula for computation of
the baud rate for different EUSARTx modes which only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
apply in Master mode (internally generated clock).
Given the desired baud rate and F
OSC
, the nearest
. From this,
the error in baud rate can be determined. An example
calculation is shown in
calculation is shown in
. Typical baud rates
and error values for the various Asynchronous modes
are shown in
are shown in
. It may be advantageous to use
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
Writing a new value to the SPBRGHx:SPBRGx
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer over-
flow before outputting the new baud rate. When
operated in Synchronous mode, SPBRGHx:SPBRGx
values of 0000h and 0001h are not supported. In the
Asynchronous mode, all BRG values may be used.
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer over-
flow before outputting the new baud rate. When
operated in Synchronous mode, SPBRGHx:SPBRGx
values of 0000h and 0001h are not supported. In the
Asynchronous mode, all BRG values may be used.
21.1.1
OPERATION IN POWER-MANAGED
MODES
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRGx register pair.
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRGx register pair.
21.1.2
SAMPLING
The data on the RXx pin (either RC7/RX1/DT1 or
RG2/RX2/DT2) is sampled three times by a majority
detect circuit to determine if a high or a low level is
present at the RXx pin.
RG2/RX2/DT2) is sampled three times by a majority
detect circuit to determine if a high or a low level is
present at the RXx pin.
TABLE 21-1:
BAUD RATE FORMULAS
Configuration Bits
BRG/EUSARTx Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
8-bit/Asynchronous
F
OSC
/[64 (n + 1)]
0
0
1
8-bit/Asynchronous
F
OSC
/[16 (n + 1)]
0
1
0
16-bit/Asynchronous
0
1
1
16-bit/Asynchronous
F
OSC
/[4 (n + 1)]
1
0
x
8-bit/Synchronous
1
1
x
16-bit/Synchronous
Legend: x
= Don’t care; n = value of SPBRGHx:SPBRGx register pair