Microchip Technology DV164136 Data Sheet
2007-2012 Microchip Technology Inc.
DS39778E-page 297
PIC18F87J11 FAMILY
21.2.2
EUSARTx ASYNCHRONOUS
RECEIVER
RECEIVER
The receiver block diagram is shown in
The data is received on the RXx pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
OSC
. This mode would typically be used
in RS-232 systems.
21.2.2.1
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero (after
accounting for the RXDTP setting). Following the Start
bit will be the Least Significant bit of the data character
being received. As each bit is received, the value will
be sampled and shifted into the Receive Shift Register
(RSR). After all 8 or 9 data bits (user-selectable option)
of the character have been shifted in, one final bit time
is measured and the level is sampled. This is the Stop
bit, which should always be a ‘1’ (after accounting for
the RXDTP setting). If the data recovery circuit
samples a ‘0’ in the Stop bit position, then a Framing
Error (FERR) is set for this character; otherwise, the
Framing Error is cleared for this character.
Once all data bits of the character and the Stop bit have
been received, the data bits in the RSR will immediately
be transferred to a two-character First-In-First-Out
(FIFO) memory. The FIFO buffering allows reception of
two complete characters before software is required to
service the EUSARTx receiver. The RSR register is not
directly accessible by software. Firmware can read
data from the FIFO by reading the RCREGx register.
Each firmware initiated read from the RCREGx register
will advance the FIFO by one character and will clear
the EUSARTx Receive Interrupt Flag (RCxIF) if no
additional data exists in the FIFO.
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero (after
accounting for the RXDTP setting). Following the Start
bit will be the Least Significant bit of the data character
being received. As each bit is received, the value will
be sampled and shifted into the Receive Shift Register
(RSR). After all 8 or 9 data bits (user-selectable option)
of the character have been shifted in, one final bit time
is measured and the level is sampled. This is the Stop
bit, which should always be a ‘1’ (after accounting for
the RXDTP setting). If the data recovery circuit
samples a ‘0’ in the Stop bit position, then a Framing
Error (FERR) is set for this character; otherwise, the
Framing Error is cleared for this character.
Once all data bits of the character and the Stop bit have
been received, the data bits in the RSR will immediately
be transferred to a two-character First-In-First-Out
(FIFO) memory. The FIFO buffering allows reception of
two complete characters before software is required to
service the EUSARTx receiver. The RSR register is not
directly accessible by software. Firmware can read
data from the FIFO by reading the RCREGx register.
Each firmware initiated read from the RCREGx register
will advance the FIFO by one character and will clear
the EUSARTx Receive Interrupt Flag (RCxIF) if no
additional data exists in the FIFO.
21.2.2.2
Receive Overrun Error
If the user firmware allows the FIFO to become full, and
a third character is received before the firmware reads
from RCREGx, a buffer Overrun Error (OERR) condition
will occur. In this case, the hardware will block the RSR
contents (the third byte received) from being copied into
the receive FIFO, the character will be lost and the
OERR status bit in the RCSTAx register will become set.
If an OERR condition is allowed to occur, firmware must
clear the condition by clearing, and then resetting
CREN, before additional characters can be successfully
received.
a third character is received before the firmware reads
from RCREGx, a buffer Overrun Error (OERR) condition
will occur. In this case, the hardware will block the RSR
contents (the third byte received) from being copied into
the receive FIFO, the character will be lost and the
OERR status bit in the RCSTAx register will become set.
If an OERR condition is allowed to occur, firmware must
clear the condition by clearing, and then resetting
CREN, before additional characters can be successfully
received.
21.2.2.3
Setting Up Asynchronous Receive
To set up an Asynchronous Reception:
1.
1.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
bit, SYNC, and setting bit, SPEN.
3.
If interrupts are desired, set enable bit, RCxIE.
4.
If 9-bit reception is desired, set bit, RX9.
5.
Enable the reception by setting bit, CREN.
6.
Flag bit, RCxIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCxIE, was set.
complete and an interrupt will be generated if
enable bit, RCxIE, was set.
7.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
enabled) and determine if any error occurred
during reception.
8.
Read the 8-bit received data by reading the
RCREGx register.
RCREGx register.
9.
If any error occurred, clear the error by clearing
enable bit, CREN.
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
set.
21.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
the SYNC bit and setting the SPEN bit.
3.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCxIP bit.
select the desired priority level with the RCxIP bit.
4.
Set the RX9 bit to enable 9-bit reception.
5.
Set the ADDEN bit to enable address detect.
6.
Enable reception by setting the CREN bit.
7.
The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
8.
Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
error occurred during reception, as well as read
bit 9 of data (if applicable).
9.
Read RCREGx to determine if the device is
being addressed.
being addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
receive buffer and interrupt the CPU.