Microchip Technology DV164136 Data Sheet

 2007-2012 Microchip Technology Inc.

DS39778E-page 317

The A/D Converter in the PIC18F87J11 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1<6>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for the offset. Thus, subsequent offsets
will be compensated. An example of a calibration
routine is shown in 

.

The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.

The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.

If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON1 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits, ACQT<2:0>, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCSx bits in the OSCCON register must have already
been cleared prior to starting the conversion.

BSF

WDTCON,ADSHR

;Enable write/read to the shared SFR

BCF

ANCON0,PCFG0

;Make Channel 0 analog

BCF

WDTCON,ADSHR

;Disable write/read to the shared SFR

BSF  

ADCON0,ADON

;Enable A/D module

BSF

ADCON1,ADCAL

;Enable Calibration

BSF

ADCON0,GO

;Start a dummy A/D conversion

CALIBRATION

;

BTFSC

ADCON0,GO

;Wait for the dummy conversion to finish

BRA

CALIBRATION

;

BCF

ADCON1,ADCAL

;Calibration done, turn off calibration enable

;Proceed with the actual A/D conversion