Microchip Technology DV164136 Data Sheet
PIC18F87J11 FAMILY
DS39778E-page 44
2007-2012 Microchip Technology Inc.
3.5.3
INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
FREQUENCY AND TUNING
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE
register (
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE
register (
).
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution
continues during this shift and there is no indication that
the shift has occurred.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution
continues during this shift and there is no indication that
the shift has occurred.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
3.5.4
INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as V
DD
or tempera-
ture changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE reg-
ister. Depending on the device, this may have no effect
on the INTRC clock source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE reg-
ister. Depending on the device, this may have no effect
on the INTRC clock source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made, and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
3.5.4.1
Compensating with the EUSARTx
An adjustment may be required when the EUSARTx
begins to generate Framing Errors or receives data
with errors while in Asynchronous mode. Framing
Errors indicate that the device clock frequency is too
high. To adjust for this, decrement the value in
OSCTUNE to reduce the clock frequency. On the other
hand, errors in data may suggest that the clock speed
is too low. To compensate, increment OSCTUNE to
increase the clock frequency.
begins to generate Framing Errors or receives data
with errors while in Asynchronous mode. Framing
Errors indicate that the device clock frequency is too
high. To adjust for this, decrement the value in
OSCTUNE to reduce the clock frequency. On the other
hand, errors in data may suggest that the clock speed
is too low. To compensate, increment OSCTUNE to
increase the clock frequency.
3.5.4.2
Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
3.5.4.3
Compensating with the CCP Module
in Capture Mode
in Capture Mode
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
3.6
Reference Clock Output
In addition to the F
OSC
/4 clock output in certain oscilla-
tor modes, the device clock in the PIC18F87J11 family
can also be configured to provide a reference clock out-
put signal to a port pin. This feature is available in all
oscillator configurations and allows the user to select a
greater range of clock sub-multiples to drive external
devices in the application.
This reference clock output is controlled by the
REFOCON register (
can also be configured to provide a reference clock out-
put signal to a port pin. This feature is available in all
oscillator configurations and allows the user to select a
greater range of clock sub-multiples to drive external
devices in the application.
This reference clock output is controlled by the
REFOCON register (
). Setting the ROON
bit (REFOCON<7>) makes the clock signal available
on the REFO (RE3) pin. The RODIV<3:0> bits enable
the selection of 16 different clock divider options.
The ROSSLP and ROSEL bits (REFOCON<5:4>) con-
trol the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode;
otherwise, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
The REFOCON register is an alternate SFR and
shares the same memory address as the OSCCON
register. It is accessed by setting the ADSHR bit in the
WDTCON register (WDTCON<4>).
on the REFO (RE3) pin. The RODIV<3:0> bits enable
the selection of 16 different clock divider options.
The ROSSLP and ROSEL bits (REFOCON<5:4>) con-
trol the availability of the reference output during Sleep
mode. The ROSEL bit determines if the oscillator on
OSC1 and OSC2, or the current system clock source,
is used for the reference clock output. The ROSSLP bit
determines if the reference source is available on RE3
when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for an EC or HS mode;
otherwise, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
The REFOCON register is an alternate SFR and
shares the same memory address as the OSCCON
register. It is accessed by setting the ADSHR bit in the
WDTCON register (WDTCON<4>).