Microchip Technology DV164136 Data Sheet
2007-2012 Microchip Technology Inc.
DS39778E-page 49
PIC18F87J11 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCSx bits are not affected by the wake-up; the Timer1
oscillator continues to run.
primary clock is providing the clock. The IDLEN and
SCSx bits are not affected by the wake-up; the Timer1
oscillator continues to run.
FIGURE 4-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 4-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q4
Q3
Q2
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
1
2
3
n-1
n
Clock Transition
Q4
Q3
Q2
Q1
Q3
Q2
PC + 4
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
T1OSI
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q2
Q3
Note 1:
T
OST
= 1024 T
OSC
; T
PLL
= 2 ms (approx). These intervals are not shown to scale.
SCS<1:0> Bits Changed
T
PLL(1)
1
2
n-1 n
Clock
OSTS Bit Set
Transition
T
OST(1)