Microchip Technology DV164136 Data Sheet
2007-2012 Microchip Technology Inc.
DS39778E-page 79
PIC18F87J11 FAMILY
6.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used
by the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of data
memory (FFFh) and extend downward to occupy more
than the top half of Bank 15 (F5Ah to FFFh). A list of these
registers is given in
by the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of data
memory (FFFh) and extend downward to occupy more
than the top half of Bank 15 (F5Ah to FFFh). A list of these
registers is given in
and
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of the
peripheral features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
peripheral features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
Addresses, F5Ah through F5Fh, are not
part of the Access Bank. These registers
must always be accessed using the Bank
Select Register. Addresses, F40h to
F59h, are not implemented and are not
accessible to the user.
part of the Access Bank. These registers
must always be accessed using the Bank
Select Register. Addresses, F40h to
F59h, are not implemented and are not
accessible to the user.
TABLE 6-3:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J11 FAMILY DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
Address
Name
FFFh
TOSU
FDFh
INDF2
FBFh
ECCP1AS
F9Fh
IPR1
F7Fh
SPBRGH1
F5Fh
PMDIN2H
FFEh
TOSH
FDEh POSTINC2
FBEh ECCP1DEL
F9Eh
PIR1
F7Eh
BAUDCON1
F5Eh
PMDIN2L
FFDh
TOSL
FDDh POSTDEC2
)
FBDh
CCPR1H
F9Dh
PIE1
F7Dh
SPBRGH2
F5Dh
PMEH
FFCh
STKPTR
FDCh
PREINC2
)
FBCh
CCPR1L
F9Ch
RCSTA2
F7Ch
BAUDCON2
F5Ch
PMEL
FFBh
PCLATU
FDBh
PLUSW2
(
)
FBBh
CCP1CON
F9Bh
OSCTUNE
F7Bh
TMR3H
F5Bh
PMSTATH
FFAh
PCLATH
FDAh
FSR2H
FBAh
ECCP2AS
F9Ah
TRISJ
)
F7Ah
TMR3L
F5Ah
PMSTATL
FF9h
PCL
FD9h
FSR2L
FB9h ECCP2DEL
F99h
TRISH
F79h
T3CON
F59h
—
FF8h
TBLPTRU
FD8h
STATUS
FB8h
CCPR2H
F98h
TRISG
F78h
TMR4
F58h
—
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
CCPR2L
F97h
TRISF
F77h
PR4
)
F57h
—
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
CCP2CON
F96h
TRISE
F76h
T4CON
F56h
—
FF5h
TABLAT
FD5h
T0CON
FB5h
ECCP3AS
F95h
TRISD
F75h
CCPR4H
F55h
—
FF4h
PRODH
FD4h
—
FB4h ECCP3DEL
F94h
TRISC
F74h
CCPR4L
F54h
—
FF3h
PRODL
FD3h
OSCCON
FB3h
CCPR3H
F93h
TRISB
F73h
CCP4CON
F53h
—
FF2h
INTCON
FD2h
CM1CON
FB2h
CCPR3L
F92h
TRISA
F72h
CCPR5H
F52h
—
FF1h
INTCON2
FD1h
CM2CON
FB1h
CCP3CON
F91h
LATJ
F71h
CCPR5L
F51h
—
FF0h
INTCON3
FD0h
RCON
FB0h
SPBRG1
F90h
LATH
F70h
CCP5CON
F50h
—
FEFh
INDF0
(
)
FCFh
TMR1H
FAFh
RCREG1
F8Fh
LATG
F6Fh
SSP2BUF
F4Fh
—
FEEh POSTINC0
(
)
FCEh
TMR1L
)
FAEh
TXREG1
F8Eh
LATF
F6Eh
SSP2ADD
F4Eh
—
FEDh POSTDEC0
)
FCDh
T1CON
FADh
TXSTA1
F8Dh
LATE
F6Dh
SSP2STAT
F4Dh
—
FECh
PREINC0
FCCh
TMR2
(
)
FACh
RCSTA1
F8Ch
LATD
F6Ch
SSP2CON1
F4Ch
—
FEBh
PLUSW0
FCBh
PR2
)
FABh
SPBRG2
F8Bh
LATC
F6Bh
SSP2CON2
F4Bh
—
FEAh
FSR0H
FCAh
T2CON
FAAh
RCREG2
F8Ah
LATB
F6Ah
CMSTAT
F4Ah
—
FE9h
FSR0L
FC9h
SSP1BUF
FA9h
TXREG2
F89h
LATA
F69h
PMADDRH
F49h
—
FE8h
WREG
FC8h
SSP1ADD
FA8h
TXSTA2
F88h
PORTJ
F68h
PMADDRL
F48h
—
FE7h
INDF1
(
)
FC7h
SSP1STAT
FA7h
EECON2
F87h
PORTH
)
F67h
PMDIN1H
F47h
—
FE6h POSTINC1
(
)
FC6h
SSP1CON1
FA6h
EECON1
F86h
PORTG
F66h
PMDIN1L
F46h
—
FE5h POSTDEC1
)
FC5h
SSP1CON2
FA5h
IPR3
F85h
PORTF
F65h
PMCONH
F45h
—
FE4h
PREINC1
FC4h
ADRESH
FA4h
PIR3
F84h
PORTE
F64h
PMCONL
F44h
—
FE3h
PLUSW1
FC3h
ADRESL
FA3h
PIE3
F83h
PORTD
F63h
PMMODEH
F43h
—
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC
F62h
PMMODEL
F42h
—
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
F61h
PMDOUT2H
F41h
—
FE0h
BSR
FC0h
WDTCON
FA0h
PIE2
F80h
PORTA
F60h
PMDOUT2L
F40h
—
Note 1:
This is not a physical register.
2:
This register is not available on 64-pin devices.
3:
This register shares the same address with another register (see
for alternate register).
4:
The PMADDRH/L and PMDOUT1H/L register pairs share the same address. PMADDR is used in Master modes and PMDOUT1 is used in
Slave modes.
Slave modes.
5:
Addresses, F40 to F59, are not implemented and are not accessible to the user.