Microchip Technology MA330018 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70291G-page 241
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
19.2
I
2
C Resources
Many useful resources related to I
2
C are provided on
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19.2.1
KEY RESOURCES
C™)”
(DS70195)
19.3
I
2
C Registers
The I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CxSTAT are
read/write:
• I2CxRSR is the shift register used for shifting data
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CxSTAT are
read/write:
• I2CxRSR is the shift register used for shifting data
internal to the module and the user application
has no access to it
has no access to it
• I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read
bytes are read
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation
• The I2CxADD register holds the slave address
• A status bit, ADD10, indicates 10-bit Address
• A status bit, ADD10, indicates 10-bit Address
mode
• The I2CxBRG acts as the Baud Rate Generator
(BRG) reload value
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
Note:
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