Microchip Technology MA330018 Data Sheet

Page of 460
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
DS70291G-page  256
© 2007-2012 Microchip Technology Inc.
21.3
Modes of Operation
The ECAN module can operate in one of several 
operation modes selected by the user. These modes 
include:
• Initialization mode
• Disable mode
• Normal Operation mode
• Listen Only mode
• Listen All Messages mode
• Loopback mode
Modes are requested by setting the REQOP<2:0> bits 
(CiCTRL1<10:8>). Entry into a mode is Acknowledged 
by monitoring the OPMODE<2:0> bits 
(CiCTRL1<7:5>). The module does not change the 
mode and the OPMODE bits until a change in mode is 
acceptable, generally during bus Idle time, which is 
defined as at least 11 consecutive recessive bits.
21.3.1
INITIALIZATION MODE
In the Initialization mode, the module does not transmit 
or receive. The error counters are cleared and the 
interrupt flags remain unchanged. The user application 
has access to Configuration registers that are access 
restricted in other modes. The module protects the user 
from accidentally violating the CAN protocol through 
programming errors. All registers which control the 
configuration of the module can not be modified while 
the module is on-line. The ECAN module is not allowed 
to enter the Configuration mode while a transmission is 
taking place. The Configuration mode serves as a lock 
to protect the following registers:
• All Module Control registers
• Baud Rate and Interrupt Configuration registers 
• Bus Timing registers 
• Identifier Acceptance Filter registers 
• Identifier Acceptance Mask registers
21.3.2
DISABLE MODE
In Disable mode, the module does not transmit or 
receive. The module has the ability to set the WAKIF bit 
due to bus activity, however, any pending interrupts 
remains and the error counters retains their value.
If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the 
module enters the Module Disable mode. If the module is 
active, the module waits for 11 recessive bits on the CAN 
bus, detect that condition as an Idle bus, then accept the 
module disable command. When the OPMODE<2:0> 
bits (CiCTRL1<7:5>) = 001, that indicates whether the 
module successfully went into Module Disable mode. 
The I/O pins reverts to normal I/O function when the 
module is in the Module Disable mode.
The module can be programmed to apply a low-pass 
filter function to the CiRX input line while the module or 
the CPU is in Sleep mode. The WAKFIL bit 
(CiCFG2<14>) enables or disables the filter.
21.3.3
NORMAL OPERATION MODE
Normal Operation mode is selected when the 
REQOP<2:0> = 000. In this mode, the module is 
activated and the I/O pins assumes the CAN bus 
functions. The module transmits and receive CAN bus 
messages via the CiTX and CiRX pins.
21.3.4
LISTEN ONLY MODE
If the Listen Only mode is activated, the module on the 
CAN bus is passive. The transmitter buffers revert to 
the port I/O function. The receive pins remain inputs. 
For the receiver, no error flags or Acknowledge signals 
are sent. The error counters are deactivated in this 
state. The Listen Only mode can be used for detecting 
the baud rate on the CAN bus. To use this, it is 
necessary that there are at least two further nodes that 
communicate with each other. 
21.3.5
LISTEN ALL MESSAGES MODE
The module can be set to ignore all errors and receive 
any message. The Listen All Messages mode is 
activated by setting the REQOP<2:0> = 111. In this 
mode, the data which is in the message assembly 
buffer, until the time an error occurred, is copied in the 
receive buffer and can be read via the CPU interface. 
21.3.6
LOOPBACK MODE
If the Loopback mode is activated, the module 
connects the internal transmit signal to the internal 
receive signal at the module boundary. The transmit 
and receive pins revert to their port I/O function.
Note:
Typically, if the ECAN module is allowed to 
transmit in a particular mode of operation 
and a transmission is requested 
immediately after the ECAN module has 
been placed in that mode of operation, the 
module waits for 11 consecutive recessive 
bits on the bus before starting 
transmission. If the user switches to 
Disable mode within this 11-bit period, 
then this transmission is aborted and the 
corresponding TXABT bit is set and 
TXREQ bit is cleared.