Microchip Technology MA330018 Data Sheet
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
DS70291G-page 26
© 2007-2012 Microchip Technology Inc.
3.6
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
R-0
R/C-0
R/C-0
R-0
R/C-0
R -0
R/W-0
OA
OB
SA
(1)
SB
(1)
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0
(3)
R/W-0
(3)
R/W-0
(3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL<2:0>
(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clear only bit
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Set only bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator (Sticky) Status bit
(4)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulators A or B are saturated
0 = Neither Accumulators A or B are saturated
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15>) = 1.
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.