Microchip Technology MA330018 Data Sheet
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
DS70291G-page 300
© 2007-2012 Microchip Technology Inc.
23.6
DAC Control Registers
REGISTER 23-1:
DAC1CON: DAC CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
DACEN
—
DACSIDL
AMPON
—
—
—
FORM
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
—
DACFDIV<6:0>
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
DACEN: DAC1 Enable bit
1 = Enables module
0 = Disables module
1 = Enables module
0 = Disables module
bit 14
Unimplemented: Read as ‘0’
bit 13
DACSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
AMPON: Enable Analog Output Amplifier in Sleep Mode/Stop-in Idle Mode bit
1 = Analog Output Amplifier is enabled during Sleep Mode/Stop-in Idle mode
0 = Analog Output Amplifier is disabled during Sleep Mode/Stop-in Idle mode
1 = Analog Output Amplifier is enabled during Sleep Mode/Stop-in Idle mode
0 = Analog Output Amplifier is disabled during Sleep Mode/Stop-in Idle mode
bit 11-9
Unimplemented: Read as ‘0’
bit 8
FORM: Data Format Select bit
1 = Signed integer
0 = Unsigned integer
1 = Signed integer
0 = Unsigned integer
bit 7
Unimplemented: Read as ‘0’
bit 6-0
DACFDIV<6:0>: DAC Clock Divider bits
1111111 = Divide input clock by 128
•
•
•
0000101 = Divide input clock by 6 (default)
•
•
•
0000010 = Divide input clock by 3
0000001 = Divide input clock by 2
0000000 = Divide input clock by 1 (no divide)
1111111 = Divide input clock by 128
•
•
•
0000101 = Divide input clock by 6 (default)
•
•
•
0000010 = Divide input clock by 3
0000001 = Divide input clock by 2
0000000 = Divide input clock by 1 (no divide)