Microchip Technology MA330018 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70291G-page 37
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
4.2
Data Address Space
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 CPU has a
separate 16 bit wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps is shown in
X04 and dsPIC33FJ128MCX02/X04 CPU has a
separate 16 bit wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps is shown in
.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices imple-
ment up to 16 Kbytes of data memory. Should an EA
point to a location outside of this area, an all-zero word
or byte is returned.
X04 and dsPIC33FJ128MCX02/X04 devices imple-
ment up to 16 Kbytes of data memory. Should an EA
point to a location outside of this area, an all-zero word
or byte is returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
AND ALIGNMENT
To maintain backward compatibility with PIC
®
MCU
devices and improve data space memory usage
efficiency, the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
effective address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] results in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
A data byte read, reads the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
efficiency, the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
effective address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] results in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
A data byte read, reads the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
4.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04
and dsPIC33FJ128MCX02/X04 core and peripheral
modules for controlling the operation of the device.
The SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04
and dsPIC33FJ128MCX02/X04 core and peripheral
modules for controlling the operation of the device.
The SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.4
NEAR DATA SPACE
The 8 Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
the MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an address pointer.
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
the MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an address pointer.
Note:
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.