Microchip Technology MA330018 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70291G-page 63
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
4.4.1
SOFTWARE STACK
In addition to its use as a working register, the W15
register in the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 devices is also used as a software Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower to higher addresses. It
pre-decrements for stack pops and post-increments for
stack pushes, as shown in
register in the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 devices is also used as a software Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower to higher addresses. It
pre-decrements for stack pops and post-increments for
stack pushes, as shown in
. For a PC push
during any CALL instruction, the MSb of the PC is
zero-extended before the push, ensuring that the MSb
is always clear.
zero-extended before the push, ensuring that the MSb
is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. The SPLIM is uninitialized at Reset. As is
the case for the Stack Pointer, the SPLIM<0> is forced
to ‘0’ because all stack operations must be word
aligned.
Whenever an EA is generated using the W15 as a
source or destination pointer, the resulting address is
compared with the value in the SPLIM register. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
ister are equal and a push operation is performed, a
stack error trap does not occur. The stack error trap
occurs on a subsequent push operation. For example,
to cause a stack error trap when the stack grows
beyond address 0x2000 in RAM, initialize the SPLIM
with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
with the Stack Pointer sets an upper address boundary
for the stack. The SPLIM is uninitialized at Reset. As is
the case for the Stack Pointer, the SPLIM<0> is forced
to ‘0’ because all stack operations must be word
aligned.
Whenever an EA is generated using the W15 as a
source or destination pointer, the resulting address is
compared with the value in the SPLIM register. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
ister are equal and a push operation is performed, a
stack error trap does not occur. The stack error trap
occurs on a subsequent push operation. For example,
to cause a stack error trap when the stack grows
beyond address 0x2000 in RAM, initialize the SPLIM
with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6:
CALL STACK FRAME
4.4.2
DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. The BSRAM (Secure
RAM segment for BS) is accessible only from the Boot
Segment Flash code when enabled. The SSRAM
(Secure RAM segment for RAM) is accessible only
from the Secure Segment Flash code when enabled.
See
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. The BSRAM (Secure
RAM segment for BS) is accessible only from the Boot
Segment Flash code when enabled. The SSRAM
(Secure RAM segment for RAM) is accessible only
from the Secure Segment Flash code when enabled.
See
for an overview of the BSRAM and
SSRAM SFRs.
4.5
Instruction Addressing Modes
The addressing modes shown in
form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.5.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.5.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where:
Operand 1 is always a working register (that is, the
addressing mode can only be register direct), which is
referred to as Wb.
addressing mode can only be register direct), which is
referred to as Wb.
Operand 2 can be a W register, fetched from data
memory, or a 5-bit literal. The result location can be
either a W register or a data memory location. The
following addressing modes are supported by MCU
instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
memory, or a 5-bit literal. The result location can be
either a W register or a data memory location. The
following addressing modes are supported by MCU
instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
concatenates the SRL register to the MSb
of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
0
15
W15 (before CALL)
W15 (after CALL)
S
tac
k Gr
ows
T
owa
rd
s
Hi
gh
er
A
dd
re
ss
0x0000
PC<22:16>
POP : [--W15]
PUSH : [W15++]
Note:
Not all instructions support all the
addressing modes listed above.
Individual instructions can support
different subsets of these addressing
modes.
addressing modes listed above.
Individual instructions can support
different subsets of these addressing
modes.