Microchip Technology MA330018 Data Sheet

© 2007-2012 Microchip Technology Inc.

DS70291G-page  89

The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 interrupt 
controller reduces the numerous peripheral interrupt 
request signals to a single interrupt request signal to 
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 CPU. 
The interrupt controller has the following features:
• Up to eight processor exceptions and software 

traps

• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception 

source

• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug 

support

• Fixed interrupt entry and return latencies

The Interrupt Vector Table (IVT) shown in 

resides in program memory, starting at location 
000004h. The IVT contains 126 vectors consisting of 
eight nonmaskable trap vectors plus up to 118 sources 
of interrupt. In general, each interrupt source has its 
own vector. Each interrupt vector contains a 24-bit wide 
address. The value programmed into each interrupt 
vector location is the starting address of the associated 
Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural 
priority. This priority is linked to their position in the 
vector table. Lower addresses generally have a higher 
natural priority. For example, the interrupt associated 
with vector 0 takes priority over interrupts at any other 
vector address.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices imple-
ment up to 53 unique interrupts and five nonmaskable 
traps. These are summarized in 

7.1.1

ALTERNATE INTERRUPT VECTOR 
TABLE

The Alternate Interrupt Vector Table (AIVT) is located 
after the IVT, as shown in 

. Access to the 

AIVT is provided by the ALTIVT control bit 
(INTCON2<15>). If the ALTIVT bit is set, all interrupt 
and exception processes use the alternate vectors 
instead of the default vectors. The alternate vectors are 
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to 
switch between an application and a support 
environment without requiring the interrupt vectors to 
be reprogrammed. This feature also enables switching 
between applications for evaluation of different 
software algorithms at run time. If the AIVT is not 
needed, the AIVT should be programmed with the 
same addresses used in the IVT.

A device Reset is not a true exception because the 
interrupt controller is not involved in the Reset process. 
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 device clears its 
registers in response to a Reset, which forces the PC 
to zero. The digital signal controller then begins 
program execution at location 0x000000. A GOTO
instruction at the Reset address can redirect program 
execution to the appropriate start-up routine.

Note 1: This data sheet summarizes the features 

of the dsPIC33FJ32MC302/304, 
dsPIC33FJ64MCX02/X04 and 
dsPIC33FJ128MCX02/X04 family of 
devices. It is not intended to be a 
comprehensive reference source. To 
complement the information in this data 
sheet, refer to Section 32. “Interrupts 
(Part III)” (DS70214) of the “dsPIC33F/
PIC24H Family Reference Manual”, 
which is available from the Microchip web 
site (

www.microchip.com

).

2: Some registers and associated bits 

described in this section may not be 
available on all devices. Refer to 

 in 

this data sheet for device-specific register 
and bit information.

Any unimplemented or unused vector 
locations in the IVT and AIVT should be 
programmed with the address of a default 
interrupt handler routine that contains a 
RESET instruction.