Microchip Technology MA240017 Data Sheet
2008-2011 Microchip Technology Inc.
DS39927C-page 137
PIC24F16KA102 FAMILY
bit 1-0
PPRE<1:0>:
Primary Prescale bits (Master mode)
11
= Primary prescale 1:1
10
= Primary prescale 4:1
01
= Primary prescale 16:1
00
= Primary prescale 64:1
REGISTER 16-2:
SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED)
Note 1:
The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
SPI modes (FRMEN = 1).
REGISTER 16-3:
SPI1CON2: SPI1 CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
SPIFPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SPIFE
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FRMEN:
Framed SPI1 Support bit
1
= Framed SPI1 support is enabled
0
= Framed SPI1 support is disabled
bit 14
SPIFSD:
Frame Sync Pulse Direction Control on SS1 Pin bit
1
= Frame sync pulse input (slave)
0
= Frame sync pulse output (master)
bit 13
SPIFPOL:
Frame Sync Pulse Polarity bit (Frame mode only)
1
= Frame sync pulse is active-high
0
= Frame sync pulse is active-low
bit 12-2
Unimplemented:
Read as ‘0’
bit 1
SPIFE:
Frame Sync Pulse Edge Select bit
1
= Frame sync pulse coincides with the first bit clock
0
= Frame sync pulse precedes the first bit clock
bit 0
SPIBEN:
Enhanced Buffer Enable bit
1
= Enhanced Buffer is enabled
0
= Enhanced Buffer is disabled (Legacy mode)