Microchip Technology MA240017 Data Sheet

 2008-2011 Microchip Technology Inc.

DS39927C-page 139

The Inter-Integrated Circuit (I

2

C) module is a serial

interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial data EEPROMs, display drivers,
A/D Converters, etc.
The I

2

C module supports these features:

• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I

2

C protocol

• Automatic clock stretching to provide delays for 

the processor to respond to a slave data request

• Both 100 kHz and 400 kHz bus specifications
• Configurable address masking
• Multi-Master modes to prevent loss of messages 

in arbitration

• Bus Repeater mode, allowing the acceptance of 

all messages as a slave regardless of the address

• Automatic SCL 

 illustrates a block diagram of the module.

The I

2

C module is tied to a fixed pin. To allow flexibility

with peripheral multiplexing, the I2C1 module in 28-pin
devices can be reassigned to the alternate pins,
designated as SCL1 and SDA1 during device
configuration. 
Pin assignment is controlled by the I2C1SEL
Configuration bit. Programming this bit (= 0) multiplexes
the module to the SCL1 and SDA1 pins.

The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.

Assert a Start condition on SDA1 and SCL1.

2.

Send the I

2

C device address byte to the slave

with a write indication.

3.

Wait for and verify an Acknowledge from the
slave.

4.

Send the first data byte (sometimes known as
the command) to the slave.

5.

Wait for and verify an Acknowledge from the
slave.

6.

Send the serial memory address low byte to the
slave.

7.

Repeat Steps 4 and 5 until all data bytes are
sent.

8.

Assert a Repeated Start condition on SDA1 and
SCL1.

9.

Send the device address byte to the slave with
a read indication.

10. Wait for and verify an Acknowledge from the

slave.

11. Enable master reception to receive serial

memory data.

12. Generate an ACK or NACK condition at the end

of a received byte of data.

13. Generate a Stop condition on SDA1 and SCL1.

This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information
on the Inter-Integrated Circuit, refer to the
“PIC24F Family Reference Manual”

,

 (DS39702).