Microchip Technology MA240017 Data Sheet
PIC24F16KA102 FAMILY
DS39927C-page 142
2008-2011 Microchip Technology Inc.
REGISTER 17-1:
I2C1CON: I2C1 CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-1 HC
R/W-0
R/W-0
R/W-0
R/W-0
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
I2CEN:
I2C1 Enable bit
1
= Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins
0
= Disables the I2C1 module; all I
2
C™ pins are controlled by port functions
bit 14
Unimplemented:
Read as ‘0’
bit 13
I2CSIDL:
Stop in Idle Mode bit
1
= Discontinues module operation when device enters an Idle mode
0
= Continues module operation in Idle mode
bit 12
SCLREL:
SCL1 Release Control bit (when operating as I
2
C slave)
1
= Releases SCL1 clock
0
= Holds SCL1 clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission; hardware is clear at the end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave
transmission.
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission; hardware is clear at the end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave
transmission.
bit 11
IPMIEN:
Intelligent Peripheral Management Interface (IPMI) Enable bit
1
= IPMI Support mode is enabled; all addresses are Acknowledged
0
= IPMI Support mode is disabled
bit 10
A10M:
10-Bit Slave Addressing bit
1
= I2C1ADD is a 10-bit slave address
0
= I2C1ADD is a 7-bit slave address
bit 9
DISSLW:
Disable Slew Rate Control bit
1
= Slew rate control is disabled
0
= Slew rate control is enabled
bit 8
SMEN:
SMBus Input Levels bit
1
= Enables I/O pin thresholds compliant with the SMBus specification
0
= Disables the SMBus input thresholds
bit 7
GCEN:
General Call Enable bit (when operating as I
2
C slave)
1
= Enables interrupt when a general call address is received in the I2C1RSR (module is enabled for
reception)
0
= General call address is disabled
bit 6
STREN:
SCL1 Clock Stretch Enable bit (when operating as I
2
C slave)
Used in conjunction with the SCLREL bit.
1
1
= Enables software or receive clock stretching
0
= Disables software or receive clock stretching