Microchip Technology MA240017 Data Sheet
PIC24F16KA102 FAMILY
DS39927C-page 144
2008-2011 Microchip Technology Inc.
REGISTER 17-2:
I2C1STAT: I2C1 STATUS REGISTER
R-0, HSC R-0, HSC
U-0
U-0
U-0
R/C-0, HS
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
bit 15
bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ACKSTAT:
Acknowledge Status bit
1
= NACK was detected last
0
= ACK was detected last
Hardware is set or clear at of Acknowledge.
bit 14
TRSTAT:
Transmit Status bit
(When operating as I
2
C™ master; applicable to master transmit operation.)
1
= Master transmit is in progress (8 bits + ACK)
0
= Master transmit is not in progress
Hardware is set at beginning of master transmission; hardware is clear at end of slave Acknowledge.
bit 13-11
Unimplemented:
Read as ‘0’
bit 10
BCL:
Master Bus Collision Detect bit
1
= A bus collision has been detected during a master operation
0
= No collision
Hardware is set at detection of bus collision.
bit 9
GCSTAT:
General Call Status bit
1
= General call address was received
0
= General call address was not received
Hardware is set when address matches general call address; hardware is clear at Stop detection.
bit 8
ADD10:
10-Bit Address Status bit
1
= 10-bit address was matched
0
= 10-bit address was not matched
Hardware is set at match of 2
nd
byte of matched 10-bit address; hardware is clear at Stop detection.
bit 7
IWCOL:
Write Collision Detect bit
1
= An attempt to write to the I2C1TRN register failed because the I
2
C module is busy
0
= No collision
Hardware is set at occurrence of write to I2C1TRN while busy (cleared by software).
bit 6
I2COV:
Receive Overflow Flag bit
1
= A byte was received while the I2C1RCV register is still holding the previous byte
0
= No overflow
Hardware is set at attempt to transfer to I2C1RCV (cleared by software).
bit 5
D/A:
Data/Address bit (when operating as I
2
C slave)
1
= Indicates that the last byte received was data
0
= Indicates that the last byte received was the device address
Hardware is clear at device address match; hardware is set by a write to I2C1TRN or by reception of slave byte.
bit 4
P:
Stop bit
1
= Indicates that a Stop bit has been detected last
0
= Stop bit was not detected last
Hardware is set or clear when Start, Repeated Start or Stop is detected.