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Microchip Technology MA240017 Data Sheet

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 2008-2011 Microchip Technology Inc.
DS39927C-page 47
PIC24F16KA102 FAMILY
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0, HC
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
PGMONLY
(
)
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ERASE
NVMOP5
(
)
NVMOP4
(
)
NVMOP3
NVMOP2
(
)
NVMOP1
(
)
NVMOP0
bit 7
bit 0
Legend:
SO = Settable Only bit
HC = Hardware Clearable bit
-n = Value at POR
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 15
WR:
 Write Control bit
1
 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once the operation is complete
0
 = Program or erase operation is complete and inactive
bit 14
WREN:
 Write Enable bit
1
 = Enable Flash program/erase operations
0
 = Inhibit Flash program/erase operations
bit 13
WRERR:
 Write Sequence Error Flag bit
1
 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0
 = The program or erase operation completed normally
bit 12
PGMONLY:
 Program Only Enable bit
)
bit 11-7
Unimplemented: 
Read as ‘0’
bit 6
ERASE: 
Erase/Program Enable bit
1
 = Perform the erase operation specified by NVMOP<5:0> on the next WR command
0
 = Perform the program operation specified by NVMOP<5:0> on the next WR command
bit 5-0
NVMOP<5:0>:
 Programming Operation Command Byte bits
(
)
Erase Operations (when ERASE bit is ‘1’):
1010xx
 = Erase entire boot block (including code-protected boot block)
)
1001xx
 = Erase entire memory (including boot block, configuration block, general block)
(
011010
 = Erase 4 rows of Flash memory
011001
 = Erase 2 rows of Flash memory
011000
 = Erase 1 row of Flash memory
0101xx
 = Erase entire configuration block (except code protection bits)
0100xx
 = Erase entire data EEPROM
(
0011xx
 = Erase entire general memory block programming operations
0001xx
 = Write 1 row of Flash memory (when ERASE bit is ‘0’)
Note 1:
All other combinations of NVMOP<5:0> are no operation.
2:
Available in ICSP™ mode only. Refer to device programming specification.
3:
The address in the Table Pointer decides which rows will be erased.
4:
This bit is used only while accessing data EEPROM.