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Microchip Technology MA240017 Data Sheet

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PIC24F16KA102 FAMILY
DS39927C-page 58
 2008-2011 Microchip Technology Inc.
REGISTER 7-1:
RCON: RESET CONTROL REGISTER
)
R/W-0, HS
R/W-0, HS
R/W-0
U-0
U-0
R/C-0, HS
R/W-0, HS
R/W-0
TRAPR
IOPUWR
SBOREN
—
—
DPSLP
CM
PMSLP
bit 15
bit 8
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-0, HS
R/W-1, HS
R/W-1, HS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’ 
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TRAPR:
 Trap Reset Flag bit
1
 = A Trap Conflict Reset has occurred
0
 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR:
 Illegal Opcode or Uninitialized W Access Reset Flag bit
1
 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0
 = An illegal opcode or uninitialized W Reset has not occurred
bit 13
SBOREN: 
Software Enable/Disable of BOR bit
1
 = BOR is turned on in software
0
 = BOR is turned off in software
bit 12-11
Unimplemented:
 Read as ‘0’
bit 10
DPSLP: 
Deep Sleep Mode Flag bit
1
 = Deep Sleep has occurred
0
 = Deep Sleep has not occurred
bit 9
CM:
 Configuration Word Mismatch Reset Flag bit
1
 = A Configuration Word Mismatch has occurred
0
 = A Configuration Word Mismatch has not occurred
bit 8
PMSLP:
 Program Memory Power During Sleep bit
1
 = Program memory bias voltage remains powered during Sleep
0
 = Program memory bias voltage is powered down during Sleep
bit 7
EXTR: 
External Reset (MCLR) Pin bit
1
 = A Master Clear (pin) Reset has occurred
0
 = A Master Clear (pin) Reset has not occurred
bit 6
SWR:
 Software Reset (Instruction) Flag bit
1
 = A RESET instruction has been executed
0
 = A RESET instruction has not been executed
bit 5
SWDTEN:
 Software Enable/Disable of WDT bit
1
 = WDT is enabled
0
 = WDT is disabled
bit 4
WDTO:
 Watchdog Timer Time-out Flag bit
1
 = WDT time-out has occurred
0
 = WDT time-out has not occurred
Note 1:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not 
cause a device Reset.
2:
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the 
SWDTEN bit setting.