Microchip Technology MA240017 Data Sheet
PIC24F16KA102 FAMILY
DS39927C-page 60
2008-2011 Microchip Technology Inc.
7.1
Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in
device Reset is chosen, as shown in
. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to
selected according to the oscillator Configuration bits.
Refer to
for
further details.
TABLE 7-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
7.2
Device Reset Times
The Reset times for various types of device Reset are
summarized in
summarized in
. Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
TABLE 7-3:
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type
Clock Source Determinant
POR
FNOSC Configuration bits
(FNOSC<10:8>)
(FNOSC<10:8>)
BOR
MCLR
COSC Control bits
(OSCCON<14:12>)
(OSCCON<14:12>)
WDTO
SWR
Reset Type
Clock Source
SYSRST Delay
System Clock
Delay
Notes
POR
EC
T
POR
+ T
PWRT
—
FRC, FRCDIV
T
POR
+ T
PWRT
T
FRC
LPRC
T
POR
+ T
PWRT
T
LPRC
ECPLL
T
POR
+ T
PWRT
T
LOCK
FRCPLL
T
POR
+ T
PWRT
T
FRC
+ T
LOCK
XT, HS, SOSC
T
POR
+ T
PWRT
T
OST
XTPLL, HSPLL
T
POR
+ T
PWRT
T
OST
+ T
LOCK
BOR
EC
T
PWRT
—
FRC, FRCDIV
T
PWRT
T
FRC
LPRC
T
PWRT
T
LPRC
ECPLL
T
PWRT
T
LOCK
FRCPLL
T
PWRT
T
FRC
+ T
LOCK
XT, HS, SOSC
T
PWRT
T
OST
XTPLL, HSPLL
T
PWRT
T
FRC
+ T
LOCK
All Others
Any Clock
—
—
None
Note 1:
T
POR
= Power-on Reset (POR) delay.
2:
T
PWRT
= 64 ms nominal if the Power-up Timer (PWRT) is enabled; otherwise, it is zero.
3:
T
FRC
and T
LPRC
= RC oscillator start-up times.
4:
T
LOCK
= PLL lock time.
5:
T
OST
= Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
6:
If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
and in such cases, FRC start-up time is valid.
Note:
For detailed operating frequency and timing specifications, see
.