Microchip Technology SW006023-3N Data Sheet
MPLAB
®
XC32 C/C++ Compiler User’s Guide
DS51686E-page 136
2012 Microchip Technology Inc.
EXAMPLE 11-2:
CORE TIMER VECTOR, IPL2SOFT
#include <xc.h>
#include <sys/attribs.h>
void __ISR(_CORE_TIMER_VECTOR, IPL2SOFT) CoreTimerHandler(void);
Example 11-2 creates an interrupt handler function for the core timer interrupt that has
an interrupt priority level of two. The compiler places a dispatch function at the
associated vector location. To reach this function, the core timer interrupt flag and
enable bits must be set, and the interrupt priority should be set to a level of two. The
compiler generates software context-saving code for this handler function.
an interrupt priority level of two. The compiler places a dispatch function at the
associated vector location. To reach this function, the core timer interrupt flag and
enable bits must be set, and the interrupt priority should be set to a level of two. The
compiler generates software context-saving code for this handler function.
EXAMPLE 11-3:
CORE SOFTWARE 0 VECTOR, IPL3SRS
#include <xc.h>
#include <sys/attribs.h>
void __ISR(_CORE_SOFTWARE_0_VECTOR,IPL3SRS)
CoreSoftwareInt0Handler(void);
Example 11-3 creates an interrupt handler function for the core software interrupt 0 that
has an interrupt priority level of three. The compiler places a dispatch function at the
associated vector location. To reach this function, the core software interrupt flag and
enable bits must be set, and the interrupt priority should be set to a level of three. The
device configuration fuses must assign Shadow Register Set 1 to interrupt priority level
three. The compiler generates code that assumes that register context will be saved in
SRS1.
has an interrupt priority level of three. The compiler places a dispatch function at the
associated vector location. To reach this function, the core software interrupt flag and
enable bits must be set, and the interrupt priority should be set to a level of three. The
device configuration fuses must assign Shadow Register Set 1 to interrupt priority level
three. The compiler generates code that assumes that register context will be saved in
SRS1.
EXAMPLE 11-4:
CORE SOFTWARE 1 VECTOR, IPL0AUTO
#include <xc.h>
#include <sys/attribs.h>
void __ISR(_CORE_SOFTWARE_1_VECTOR, IPL0AUTO)
CoreSoftwareInt1Handler(void);
Example 11-4 creates an interrupt handler function for the core software interrupt 1 that
has an interrupt priority level of zero. The compiler places a dispatch function at the
associated vector location. To reach this function, the core software interrupt 1 flag and
enable bits must be set, and the interrupt priority should be set to a level of zero. The
compiler generates code that determines at run time whether software context saving
is required.
has an interrupt priority level of zero. The compiler places a dispatch function at the
associated vector location. To reach this function, the core software interrupt 1 flag and
enable bits must be set, and the interrupt priority should be set to a level of zero. The
compiler generates code that determines at run time whether software context saving
is required.
EXAMPLE 11-5:
CORE SOFTWARE 1 VECTOR, DEFAULT
#include <xc.h>
#include <sys/attribs.h>
void __ISR(_CORE_SOFTWARE_1_VECTOR) _CoreSoftwareInt1Handler(void);
Example 11-5 is functionally equivalent to Example 3. Because the IPL specifier is
omitted, the compiler assumes IPL0AUTO.
omitted, the compiler assumes IPL0AUTO.
11.3.3.2
__ISR_AT_VECTOR(v, IPL)
Use the __ISR_AT_VECTOR(v, IPL) to place the entire interrupt handler at the
vector location and associate it with the software-assigned interrupt priority. Application
code is responsible for making sure that the vector spacing is set to accommodate the
size of the handler. This macro also applies the nomips16 attribute since ISR functions
are required to be MIPS32.
vector location and associate it with the software-assigned interrupt priority. Application
code is responsible for making sure that the vector spacing is set to accommodate the
size of the handler. This macro also applies the nomips16 attribute since ISR functions
are required to be MIPS32.