Microchip Technology SW006023-2N Data Sheet
Main, Runtime Start-up and Reset
2012 Microchip Technology Inc.
DS51686E-page 149
FIGURE 12-4:
BUS MATRIX INITIALIZATION
12.3.5.1
INITIALIZE CP0 REGISTERS
The CP0 registers are initialized in the following order:
1.
Count
register
2.
Compare
register
3.
EBase
register
4.
IntCtl
register
5.
Cause
register
6.
Status
register
12.3.5.2
HARDWARE ENABLE REGISTER (HWREna – CP0 REGISTER 7,
SELECT 0)
SELECT 0)
This register contains a bit mask that determines which hardware registers are
accessible via the RDHWR instruction. Privileged software may determine which of the
hardware registers are accessible by the RDHWR instruction. In doing so, a register may
be virtualized at the cost of handling a Reserved Instruction Exception, interpreting the
instruction, and returning the virtualized value. For example, if it is not desirable to
provide direct access to the Count register, access to the register may be individually
disabled, and the return value can be virtualized by the operating system.
accessible via the RDHWR instruction. Privileged software may determine which of the
hardware registers are accessible by the RDHWR instruction. In doing so, a register may
be virtualized at the cost of handling a Reserved Instruction Exception, interpreting the
instruction, and returning the virtualized value. For example, if it is not desirable to
provide direct access to the Count register, access to the register may be individually
disabled, and the return value can be virtualized by the operating system.
No initialization is performed on this register in the PIC32MX start-up code.
12.3.5.3
BAD VIRTUAL ADDRESS REGISTER (BadVAddr – CP0 REGISTER 8,
SELECT 0)
SELECT 0)
This register is a read-only register that captures the most recent virtual address that
caused an Address Error exception (AdEL or AdES).
caused an Address Error exception (AdEL or AdES).
No initialization is performed on this register in the PIC32MX start-up code.