Microchip Technology SW006023-2N Data Sheet
Main, Runtime Start-up and Reset
2012 Microchip Technology Inc.
DS51686E-page 151
12.3.5.8
SHADOW REGISTER CONTROL REGISTER (SRSCtl – CP0 REGISTER
12, SELECT 2)
12, SELECT 2)
This register controls the operation of the GPR shadow sets in the processor.
No initialization is performed on this register in the PIC32MX start-up code.
12.3.5.9
SHADOW REGISTER MAP REGISTER (SRSMap – CP0 REGISTER 12,
SELECT 3)
SELECT 3)
This register contains eight 4-bit fields that provide the mapping from a vector number
to the shadow set number to use when servicing such an interrupt. The values from this
register are not used for a non-interrupt exception, or a non-vectored interrupt
(Cause
to the shadow set number to use when servicing such an interrupt. The values from this
register are not used for a non-interrupt exception, or a non-vectored interrupt
(Cause
IV
= 0
or IntCtl
VS
= 0
). In such cases, the shadow set number comes from
SRSCtlESS
. If SRSCtlHSS is zero, the results of a software read or write of this
register are UNPREDICTABLE. The operation of the processor is UNDEFINED if a
value is written to any field in this register that is greater than the value of SRSCtlHSS.
The SRSMap register contains the shadow register set numbers for vector numbers
7..0. The same shadow set number can be established for multiple interrupt vectors,
creating a many-to-one mapping from a vector to a single shadow register set number.
value is written to any field in this register that is greater than the value of SRSCtlHSS.
The SRSMap register contains the shadow register set numbers for vector numbers
7..0. The same shadow set number can be established for multiple interrupt vectors,
creating a many-to-one mapping from a vector to a single shadow register set number.
No initialization is performed on this register in the PIC32MX start-up code.
12.3.5.10 CAUSE REGISTER (Cause – CP0 REGISTER 13, SELECT 0)
This register primarily describes the cause of the most recent exception. In addition,
fields also control software interrupt requests and the vector through which interrupts
are dispatched. With the exception of the DC, IV, and IP1..IP0 fields, all fields in the
Cause
fields also control software interrupt requests and the vector through which interrupts
are dispatched. With the exception of the DC, IV, and IP1..IP0 fields, all fields in the
Cause
register are read-only. Release 2 of the Architecture added optional support for
an External Interrupt Controller (EIC) interrupt mode, in which IP7..IP2 are
interpreted as the Requested Interrupt Priority Level (RIPL).
interpreted as the Requested Interrupt Priority Level (RIPL).
The following settings are initialized by the PIC32MX start-up code:
• Enable counting of Count register (DC = no change)
• Use the special exception vector (16#200) (IV = 1)
• Disable software interrupt requests (IP1..IP0 = 0)
12.3.5.11 EXCEPTION PROGRAM COUNTER (EPC – CP0 REGISTER 14, SELECT
0)
This register is a read/write register that contains the address at which processing
resumes after an exception has been serviced. All bits of the EPC register are
significant and must be writable. For synchronous (precise) exceptions, the EPC
contains one of the following:
resumes after an exception has been serviced. All bits of the EPC register are
significant and must be writable. For synchronous (precise) exceptions, the EPC
contains one of the following:
• The virtual address of the instruction that was the direct cause of the exception
• The virtual address of the immediately preceding branch or jump instruction, when
the exception causing instruction is a branch delay slot and the Branch Delay
bit in the Cause register is set.
bit in the Cause register is set.
On new exceptions, the processor does not write to the EPC register when the EXL bit
in the Status register is set; however, the register can still be written via the MTC0
instruction.
in the Status register is set; however, the register can still be written via the MTC0
instruction.
No initialization is performed on this register in the PIC32MX start-up code.