Microchip Technology MA320002 Data Sheet

2011 Micr

och

ip T
e

chn

logy Inc.

1143H-p

age 65

PIC32MX3XX/4XX

TABLE 4-16:

DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX
DEVICES ONLY

(1)

irtual A

ddress

(BF88_#

)

Regis

ter

Bit Range

Bits

All

Reset

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

3060

DCH0CON

31:16

—

0000

15:0

—

CHCHNS

CHEN

CHAED

CHCHN

CHAEN

—

CHEDET

CHPRI<1:0>

0000

3070 DCH0ECON

31:16

—

CHAIRQ<7:0>

00FF

15:0

CHSIRQ<7:0>

CFORCE

CABORT

PATEN

SIRQEN

AIRQEN

—

FF00

3080

DCH0INT

31:16

—

CHSDIE

CHSHIE

CHDDIE

CHDHIE

CHBCIE

CHCCIE

CHTAIE

CHERIE

0000

15:0

—

CHSDIF

CHSHIF

CHDDIF

CHDHIF

CHBCIF

CHCCIF

CHTAIF

CHERIF

0000

3090

DCH0SSA

31:16

CHSSA<31:0>

0000

15:0

0000

30A0

DCH0DSA

31:16

CHDSA<31:0>

0000

15:0

0000

30B0 DCH0SSIZ

31:16

—

0000

15:0

—

CHSSIZ<7:0>

0000

30C0 DCH0DSIZ

31:16

—

0000

15:0

—

CHDSIZ<7:0>

0000

30D0 DCH0SPTR

31:16

—

0000

15:0

—

CHSTR<7:0>

0000

30E0 DCH0DPTR

31:16

—

0000

15:0

—

CHDPTR<7:0>

0000

30F0 DCH0CSIZ

31:16

—

0000

15:0

—

CHCSIZ<7:0>

0000

3100 DCH0CPTR

31:16

—

0000

15:0

—

CHCPTR<7:0>

0000

3110

DCH0DAT

31:16

—

0000

15:0

—

CHPDAT<7:0>

0000

3120

DCH1CON

31:16

—

0000

15:0

—

CHCHNS

CHEN

CHAED

CHCHN

CHAEN

—

CHEDET

CHPRI<1:0>

0000

3130 DCH1ECON

31:16

—

CHAIRQ<7:0>

00FF

15:0

CHSIRQ<7:0>

CFORCE

CABORT

PATEN

SIRQEN

AIRQEN

—

FF00

3140

DCH1INT

31:16

—

CHSDIE

CHSHIE

CHDDIE

CHDHIE

CHBCIE

CHCCIE

CHTAIE

CHERIE

0000

15:0

—

CHSDIF

CHSHIF

CHDDIF

CHDHIF

CHBCIF

CHCCIF

CHTAIF

CHERIF

0000

3150

DCH1SSA

31:16

CHSSA<31:0>

0000

15:0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR,

SET and INV Registers”

for more information.