Microchip Technology MA320002 Data Sheet

PIC32MX3XX/4XX

DS61143H

-page 74

2011 Microchip T

chnolo

y Inc.

TABLE 4-29:

PORTF REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES
ONLY

(1)

irtual A

ddress

(BF88_#

)

Regis

ter

Bit Range

Bits

All

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6140

TRISF

31:16

—

0000

15:0

—

TRISF13

TRISF12

—

TRISF8

TRISF7

TRISF6

TRISF5

TRISF4

TRISF3

TRISF2

TRISF1

TRISF0

31FF

6150

PORTF

31:16

—

0000

15:0

—

RF13

RF12

—

RF8

RF7

RF6

RF5

RF4

RF3

RF2

RF1

RF0

xxxx

6160

LATF

31:16

—

0000

15:0

—

LATF13

LATF12

—

LATF8

LATF7

LATF6

LATF5

LATF4

LATF3

LATF2

LATF1

LATF0

xxxx

6170

ODCF

31:16

—

0000

15:0

—

ODCF13

ODCF12

—

ODCF8

ODCF7

ODCF6

ODCF5

ODCF4

ODCF3

ODCF2

ODCF1

ODCF0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.

TABLE 4-30:

PORTF REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY

(1)

irtual Address

(BF88_#

)

Regis

ter

Name

Bit Range

Bits

All Re

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6140

TRISF

31:16

—

0000

15:0

—

TRISF13

TRISF12

—

TRISF8

—

TRISF5

TRISF4

TRISF3

TRISF2

TRISF1

TRISF0

313F

6150

PORTF

31:16

—

0000

15:0

—

RF13

RF12

—

RF8

—

RF5

RF4

RF3

RF2

RF1

RF0

xxxx

6160

LATF

31:16

—

0000

15:0

—

LATF13

LATF12

—

LATF8

—

LATF5

LATF4

LATF3

LATF2

LATF1

LATF0

xxxx

6170

ODCF

31:16

—

0000

15:0

—

ODCF13

ODCF12

—

ODCF8

—

ODCF5

ODCF4

ODCF3

ODCF2

ODCF1

ODCF0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.