Microchip Technology MA320002 Data Sheet

PIC32MX3XX/4XX

DS61143H

-page 72

2011 Microchip T

chnolo

y Inc.

TABLE 4-25:

PORTD REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY

(1)

irtual A

ddress

(BF88_#

)

Regis

ter

Bit Range

Bits

All

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

60C0

TRISD

31:16

—

0000

15:0

TRISD15

TRISD14

TRISD13

TRISD12

TRISD11

TRISD10

TRISD9

TRISD8

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

FFFF

60D0

PORTD

31:16

—

0000

15:0

RD15

RD14

RD13

RD12

RD11

RD10

RD9

RD8

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx

60E0

LATD

31:16

—

0000

15:0

LATD15

LATD14

LATD13

LATD12

LATD11

LATD10

LATD9

LATD8

LATD7

LATD6

LATD5

LATD4

LATD3

LATD2

LATD1

LATD0

xxxx

60F0

ODCD

31:16

—

0000

15:0

ODCD15

ODCD14

ODCD13

ODCD12

ODCD11

ODCD10

ODCD9

ODCD8

ODCD7

ODCD6

ODCD5

ODCD4

ODCD3

ODCD2

ODCD1

ODCD0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.

TABLE 4-26:

PORTD REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H
DEVICES ONLY

(1)

irtual Address

(BF88_#

)

Regis

ter

Name

Bit Range

Bits

All Re

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

60C0

TRISD

31:16

—

0000

15:0

—

TRISD11

TRISD10

TRISD9

TRISD8

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

0FFF

60D0

PORTD

31:16

—

0000

15:0

—

RD11

RD10

RD9

RD8

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx

60E0

LATD

31:16

—

0000

15:0

—

LATD11

LATD10

LATD9

LATD8

LATD7

LATD6

LATD5

LATD4

LATD3

LATD2

LATD1

LATD0

xxxx

60F0

ODCD

31:16

—

0000

15:0

—

ODCD11

ODCD10

ODCD9

ODCD8

ODCD7

ODCD6

ODCD5

ODCD4

ODCD3

ODCD2

ODCD1

ODCD0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.