Microchip Technology MA330017 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70283K-page 193
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
19.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
(UART)
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 device family. The UART is a
full-duplex asynchronous system that can
communicate with peripheral devices, such as
personal computers, LIN, and RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA
(UART) module is one of the serial I/O modules
available in the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 device family. The UART is a
full-duplex asynchronous system that can
communicate with peripheral devices, such as
personal computers, LIN, and RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA
®
encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-bit or 9-bit Data Transmission
• Full-Duplex, 8-bit or 9-bit Data Transmission
through the UxTX and UxRX pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or two stop bits
• Hardware flow control option with UxCTS and
• One or two stop bits
• Hardware flow control option with UxCTS and
UxRTS pins
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates ranging from 10 Mbps to 38 bps at 40
MIPS
• 4-deep First-In First-Out (FIFO) Transmit Data
buffer
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA
®
encoder and decoder logic
• 16x baud clock output for IrDA
®
support
A simplified block diagram of the UART module is
shown in
shown in
. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 17. “UART” (DS70188) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the Micro-
chip web site (
dsPIC33FJ16MC304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section 17. “UART” (DS70188) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on the Micro-
chip web site (
www.microchip.com
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
UxRX
Hardware Flow Control
UART Receiver
UART Transmitter
UxTX
Baud Rate Generator
UxRTS/BCLK
IrDA
®
UxCTS