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Microchip Technology MA330031-2 Data Sheet

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 2011-2013 Microchip Technology Inc.
DS70000657H-page 133
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER
(
)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
VAR
—
US1
US0
EDT
DL2
DL1
DL0
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-0
R/C-0
R-0
R/W-0
R/W-0
SATA
SATB
SATDW
ACCSAT
IPL3
(
SFA
RND
IF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’= Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
VAR:
 Variable Exception Processing Latency Control bit
1
 = Variable exception processing is enabled
0
 = Fixed exception processing is enabled
bit 3
IPL3:
 CPU Interrupt Priority Level Status bit 3
)
1
 = CPU Interrupt Priority Level is greater than 7
0
 = CPU Interrupt Priority Level is 7 or less
Note 1:
For complete register details, see 
.
2:
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.