Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 134
2011-2013 Microchip Technology Inc.
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NSTDIS
OVAERR
(
)
OVBERR
(
)
COVAERR
(
COVBERR
(
)
OVATE
(
)
OVBTE
(
)
COVTE
(
)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SFTACERR
(
)
DIV0ERR
DMACERR
MATHERR
ADDRERR
STKERR
OSCFAIL
—
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
NSTDIS:
Interrupt Nesting Disable bit
1
= Interrupt nesting is disabled
0
= Interrupt nesting is enabled
bit 14
OVAERR:
Accumulator A Overflow Trap Flag bit
(
)
1
= Trap was caused by overflow of Accumulator A
0
= Trap was not caused by overflow of Accumulator A
bit 13
OVBERR:
Accumulator B Overflow Trap Flag bit
(
)
1
= Trap was caused by overflow of Accumulator B
0
= Trap was not caused by overflow of Accumulator B
bit 12
COVAERR:
Accumulator A Catastrophic Overflow Trap Flag bit
1
= Trap was caused by catastrophic overflow of Accumulator A
0
= Trap was not caused by catastrophic overflow of Accumulator A
bit 11
COVBERR:
Accumulator B Catastrophic Overflow Trap Flag bit
1
= Trap was caused by catastrophic overflow of Accumulator B
0
= Trap was not caused by catastrophic overflow of Accumulator B
bit 10
OVATE:
Accumulator A Overflow Trap Enable bit
(
1
= Trap overflow of Accumulator A
0
= Trap is disabled
bit 9
OVBTE:
Accumulator B Overflow Trap Enable bit
(
)
1
= Trap overflow of Accumulator B
0
= Trap is disabled
bit 8
COVTE:
Catastrophic Overflow Trap Enable bit
(
)
1
= Trap on catastrophic overflow of Accumulator A or B is enabled
0
= Trap is disabled
bit 7
SFTACERR:
Shift Accumulator Error Status bit
(
1
= Math error trap was caused by an invalid accumulator shift
0
= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR:
Divide-by-Zero Error Status bit
1
= Math error trap was caused by a divide-by-zero
0
= Math error trap was not caused by a divide-by-zero
bit 5
DMACERR:
DMAC Trap Flag bit
1
= DMAC trap has occurred
0
= DMAC trap has not occurred
Note 1:
These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.