Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 141
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 8-2:
DMA CONTROLLER BLOCK DIAGRAM
8.1
DMA Resources
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8.1.1
KEY RESOURCES
• Section 22. “Direct Memory Access (DMA)”
(DS70348) in the “dsPIC33/PIC24 Family
Reference Manual”
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual”
Sections
• Development Tools
8.2
DMAC Registers
Each DMAC Channel x (where x = 0 through 3)
contains the following registers:
• 16-Bit DMA Channel Control register (DMAxCON)
• 16-Bit DMA Channel IRQ Select register (DMAxREQ)
• 32-Bit DMA RAM Primary Start Address register
contains the following registers:
• 16-Bit DMA Channel Control register (DMAxCON)
• 16-Bit DMA Channel IRQ Select register (DMAxREQ)
• 32-Bit DMA RAM Primary Start Address register
(DMAxSTA)
• 32-Bit DMA RAM Secondary Start Address register
(DMAxSTB)
• 16-Bit DMA Peripheral Address register (DMAxPAD)
• 14-Bit DMA Transfer Count register (DMAxCNT)
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA and DSADR) are common to all
DMAC channels. These status registers provide infor-
mation on write and request collisions, as well as on
last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
• 14-Bit DMA Transfer Count register (DMAxCNT)
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA and DSADR) are common to all
DMAC channels. These status registers provide infor-
mation on write and request collisions, as well as on
last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
CPU
Arbiter
Peripheral
Non-DMA
DMA X-Bus
Peripheral Indirect Address
DM
A
Cont
ro
l
DMA Controller
DMA
CPU Peripheral X-Bus
IRQ to DMA
and Interrupt
Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
0 1 2 3
SRAM
Channels
Peripheral 1
DMA
Ready
CPU
DMA
Peripheral 3
DMA
Ready
CPU
DMA
Peripheral 2
DMA
Ready
CPU
DMA
Note:
CPU and DMA address buses are not shown for clarity.
Note:
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