Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 149
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 8-12:
DMARQC: DMA REQUEST COLLISION STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
RQCOL3
RQCOL2
RQCOL1
RQCOL0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
Unimplemented:
Read as ‘0’
bit 3
RQCOL3:
DMA Channel 3 Transfer Request Collision Flag bit
1
= User force and interrupt-based request collision is detected
0
= No request collision is detected
bit 2
RQCOL2:
DMA Channel 2 Transfer Request Collision Flag bit
1
= User force and interrupt-based request collision is detected
0
= No request collision is detected
bit 1
RQCOL1:
DMA Channel 1 Transfer Request Collision Flag bit
1
= User force and interrupt-based request collision is detected
0
= No request collision is detected
bit 0
RQCOL0:
DMA Channel 0 Transfer Request Collision Flag bit
1
= User force and interrupt-based request collision is detected
0
= No request collision is detected