Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 211
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 13-2:
TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
(
)
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
—
TGATE
(
)
TCKPS1
)
TCKPS0
—
—
TCS
,
)
—
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON:
Timery On bit
(
1
= Starts 16-bit Timery
0
= Stops 16-bit Timery
bit 14
Unimplemented:
Read as ‘0’
bit 13
TSIDL:
Timery Stop in Idle Mode bit
(
)
1
= Discontinues module operation when device enters Idle mode
0
= Continues module operation in Idle mode
bit 12-7
Unimplemented:
Read as ‘0’
bit 6
TGATE:
Timery Gated Time Accumulation Enable bit
(
)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1
This bit is ignored.
When TCS = 0:
1
= Gated time accumulation is enabled
0
= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>:
Timery Input Clock Prescale Select bits
(
)
11
= 1:256
10
= 1:64
01
= 1:8
00
= 1:1
bit 3-2
Unimplemented:
Read as ‘0’
bit 1
TCS:
Timery Clock Source Select bit
)
1
= External clock is from pin, TyCK (on the rising edge)
0
= Internal clock (F
P
)
bit 0
Unimplemented:
Read as ‘0’
Note 1:
When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
functions are set through TxCON.
2:
When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
bit must be cleared to operate the 32-bit timer in Idle mode.
3:
The TyCK pin is not available on all timers. See the “
section for the available pins.