Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 213
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
14.0
INPUT CAPTURE
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices support
four input capture channels.
Key features of the input capture module include:
• Hardware-configurable for 32-bit operation in all
requiring frequency (period) and pulse measurement.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices support
four input capture channels.
Key features of the input capture module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 19 user-selectable
Trigger/Sync sources available
Trigger/Sync sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to six clock sources available for each module,
• Up to six clock sources available for each module,
driving a separate internal 16-bit counter
FIGURE 14-1:
INPUT CAPTURE x MODULE BLOCK DIAGRAM
Note 1:
This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Input Capture”
(DS70352) in the “dsPIC33/dsPIC24
Family Reference Manual
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Input Capture”
(DS70352) in the “dsPIC33/dsPIC24
Family Reference Manual
”, which is
available from the Microchip web site
(
(
www.microchip.com
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
ICxBUF
4-Level FIFO Buffer
ICx Pin
ICM<2:0>
Set ICxIF
Edge Detect Logic
ICI<1:0>
ICOV, ICBNE
Interrupt
Logic
System Bus
Prescaler
Counter
1:1/4/16
1:1/4/16
and
Clock Synchronizer
Event and
Trigger and
Sync Logic
Clock
Select
IC Clock
Sources
Sources
Trigger and
Sync Sources
Sync Sources
ICTSEL<2:0>
SYNCSEL<4:0>
Trigger
Trigger
(1)
16
16
16
ICxTMR
Increment
Reset
Note
1:
The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the Trigger/Sync source must be changed to another source option.
proper ICx module operation or the Trigger/Sync source must be changed to another source option.
PTG Trigger
Input
CTMU Edge
Control Logic