Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 222
2011-2013 Microchip Technology Inc.
bit 3
TRIGMODE:
Trigger Status Mode Select bit
1
= TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0
= TRIGSTAT is cleared only by software
bit 2-0
OCM<2:0>:
Output Compare x Mode Select bits
111
= Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when
OCxTMR = OCxRS
)
110
= Edge-Aligned PWM mode: Output set high when OCxTMR = 0 and set low when OCxTMR = OCxR
)
101
= Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100
= Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011
= Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010
= Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces
OCx pin low
001
= Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces
OCx pin high
000
= Output compare channel is disabled
REGISTER 15-1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
Note 1:
OCxR and OCxRS are double-buffered in PWM mode only.
2:
Each Output Compare x module (OCx) has one PTG clock source. See
Section 24.0 “Peripheral Trigger
Generator (PTG) Module”
for more information.
PTGO4 = OC1
PTGO5 = OC2
PTGO6 = OC3
PTGO7 = OC4
PTGO5 = OC2
PTGO6 = OC3
PTGO7 = OC4