Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 227
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 16-1:
HIGH-SPEED PWMx MODULE ARCHITECTURAL OVERVIEW
CPU
PWM
Generator 1
PWM
Generator 3
SYNCI1
SYNCO1
PWM1H
PWM1L
PWM1 Interrupt
(1)
PWM2H
PWM2L
PWM2 Interrupt
(1)
PWM3H
PWM3L
PWM3 Interrupt
(1)
Synchronization Signal
Data Bus
ADC Module
FLT1-FLT4, FLT32
Synchronization Signal
Synchronization Signal
Primary Trigger
Primary Special
DTCMP1-DTCMP3
Fault, Current-Limit and
Dead-Time Compensation
Event Trigger
Master Time Base
Fault, Current-Limit
and Dead-Time Compensation
Fault, Current-Limit
and Dead-Time Compensation
F
OSC
Note
1:
The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM”
(DS70645) for more information.
given PWM generator. Refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM”
(DS70645) for more information.
PWM
Generator 2