Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 226
2011-2013 Microchip Technology Inc.
16.1.2
WRITE-PROTECTED REGISTERS
On dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X devices, write protection is
implemented for the IOCONx and FCLCONx registers.
The write protection feature prevents any inadvertent
writes to these registers. This protection feature can be
controlled by the PWMLOCK Configuration bit
(FOSCSEL<6>). The default state of the write
protection feature is enabled (PWMLOCK = 1). The
write protection feature can be disabled by configuring,
PWMLOCK = 0.
PIC24EPXXXMC20X devices, write protection is
implemented for the IOCONx and FCLCONx registers.
The write protection feature prevents any inadvertent
writes to these registers. This protection feature can be
controlled by the PWMLOCK Configuration bit
(FOSCSEL<6>). The default state of the write
protection feature is enabled (PWMLOCK = 1). The
write protection feature can be disabled by configuring,
PWMLOCK = 0.
To gain write access to these locked registers, the user
application must write two consecutive values of
(0xABCD and 0x4321) to the PWMKEY register to
perform the unlock operation. The write access to the
IOCONx or FCLCONx registers must be the next SFR
access following the unlock process. There can be no
other SFR accesses during the unlock process and
subsequent write access. To write to both the IOCONx
and FCLCONx registers requires two unlock operations.
The correct unlocking sequence is described in
application must write two consecutive values of
(0xABCD and 0x4321) to the PWMKEY register to
perform the unlock operation. The write access to the
IOCONx or FCLCONx registers must be the next SFR
access following the unlock process. There can be no
other SFR accesses during the unlock process and
subsequent write access. To write to both the IOCONx
and FCLCONx registers requires two unlock operations.
The correct unlocking sequence is described in
.
EXAMPLE 16-1:
PWMx WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
; FLT32 pin must be pulled low externally in order to clear and disable the fault
; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd,w10
; Load first unlock key to w10 register
mov #0x4321,w11
; Load second unlock key to w11 register
mov #0x0000,w0
; Load desired value of FCLCON1 register in w0
mov w10, PWMKEY
; Write first unlock key to PWMKEY register
mov w11, PWMKEY
; Write second unlock key to PWMKEY register
mov w0,FCLCON1
; Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register
; Writing to IOCON1 register requires unlock sequence
mov #0xabcd,w10
; Load first unlock key to w10 register
mov #0x4321,w11
; Load second unlock key to w11 register
mov #0xF000,w0
; Load desired value of IOCON1 register in w0
mov w10, PWMKEY
; Write first unlock key to PWMKEY register
mov w11, PWMKEY
; Write second unlock key to PWMKEY register
mov w0,IOCON1
; Write desired value to IOCON1 register