Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 270
2011-2013 Microchip Technology Inc.
REGISTER 18-2:
SPI
X
CON1: SPI
X
CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP
MSTEN
SPRE2
(
)
SPRE1
(
)
SPRE0
)
PPRE1
PPRE0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented:
Read as ‘0’
bit 12
DISSCK:
Disable SCKx Pin bit (SPIx Master modes only)
1
= Internal SPIx clock is disabled, pin functions as I/O
0
= Internal SPIx clock is enabled
bit 11
DISSDO:
Disable SDOx Pin bit
1
= SDOx pin is not used by the module; pin functions as I/O
0
= SDOx pin is controlled by the module
bit 10
MODE16:
Word/Byte Communication Select bit
1
= Communication is word-wide (16 bits)
0
= Communication is byte-wide (8 bits)
bit 9
SMP:
SPIx Data Input Sample Phase bit
Master mode:
1
1
= Input data is sampled at end of data output time
0
= Input data is sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
SMP must be cleared when SPIx is used in Slave mode.
bit 8
CKE:
SPIx Clock Edge Select bit
(
)
1
= Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)
0
= Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
bit 7
SSEN:
Slave Select Enable bit (Slave mode)
1
= SSx pin is used for Slave mode
0
= SSx pin is not used by the module; pin is controlled by port function
bit 6
CKP:
Clock Polarity Select bit
1
= Idle state for clock is a high level; active state is a low level
0
= Idle state for clock is a low level; active state is a high level
bit 5
MSTEN:
Master Mode Enable bit
1
= Master mode
0
= Slave mode
Note 1:
The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2:
This bit must be cleared when FRMEN = 1.
3:
Do not set both primary and secondary prescalers to the value of 1:1.