Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 272
2011-2013 Microchip Technology Inc.
REGISTER 18-3:
SPI
X
CON2: SPI
X
CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
FRMDLY
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FRMEN:
Framed SPIx Support bit
1
= Framed SPIx support is enabled (SSx pin is used as Frame Sync pulse input/output)
0
= Framed SPIx support is disabled
bit 14
SPIFSD:
Frame Sync Pulse Direction Control bit
1
= Frame Sync pulse input (slave)
0
= Frame Sync pulse output (master)
bit 13
FRMPOL:
Frame Sync Pulse Polarity bit
1
= Frame Sync pulse is active-high
0
= Frame Sync pulse is active-low
bit 12-2
Unimplemented:
Read as ‘0’
bit 1
FRMDLY:
Frame Sync Pulse Edge Select bit
1
= Frame Sync pulse coincides with first bit clock
0
= Frame Sync pulse precedes first bit clock
bit 0
SPIBEN:
Enhanced Buffer Enable bit
1
= Enhanced buffer is enabled
0
= Enhanced buffer is disabled (Standard mode)